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The first item, is once again, a 4-KiB aligned physical address. Unlike previously, however, the address is not that of a page table, but instead a 4 KiB block of physical memory that is then mapped to that location in the page table and directory.
 
The Global, or 'G' above, flag, if set, prevents the [[TLB]] from updating the address in it'sits cache if CR3 is reset. Note, that the page global enable bit in CR4 must be set to enable this feature.
 
If the Dirty flag ('D') is set, then the page has been written to. This flag is not updated by the CPU, and once set will not unset itself.
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