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PCI IDE Controller: Difference between revisions

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PCI IDE Controller (view source)

Revision as of 15:26, 12 July 2013

10 bytes added ,  10 years ago
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Changed "drive" to "controller"
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m (moved IDE to PCI IDE Controller: All of the information in the article applies only to PCI IDE Controllers, not legacy IDE controllers.)
m (Changed "drive" to "controller")
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===Detecting an IDE drive===
Each IDE drivecontroller appears as a device on the [[PCI]] bus. If the class code is 0x01 (Mass Storage Controller) and the subclass code is 0x1, (IDE) this device is an IDE Device.
The IDE device only uses five BARs out of the six
* BAR0: Base address of primary channel (I/O space), if it is 0x0 or 0x1, the port is 0x1F0.
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* BAR4: Bus Master IDE; refers to the base of I/O range consisting of 16 ports. Each 8 ports controls DMA on the primary and secondary channel respectively.
 
A parallel IDE drivecontroller will use IRQs 14 and 15; a serial IDE uses only one IRQ. To read this IRQ, we look through the device's PCI configuration space:
<source lang="c">
outl((1 << 31) | (bus << 16) | (device << 11) | (func << 8) | 8, 0xCF8); // Send the parameters.
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