PCI IDE Controller: Difference between revisions

IDE is a keyword which refers to the electrical specification of the cables which connect ATA drives (like hard drives) to another device. The drives use the ATA (Advanced Technology Attachment) interface. An IDE cable also can terminate at an IDE card connected to PCI.

 

 

 

* Primary Master Drive.

* Primary Slave Drive.

* Secondary Master Drive.

* Secondary Slave Drive.

 

* Primary Master, also called SATA1.

* Primary Slave, also called SATA2.

* Secondary Master, also called SATA3.

* Secondary Slave, also called SATA4.

 

To initialise the IDE driver, we call ide_initialise:

void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,

unsigned int BAR4) {

If you only want to support the parallel IDE, you can use these parameters:

We can assume that BAR4 is 0x0 because we are not going to use it yet.

We will return to ide_initialize, which searches for drives connected to the IDE. Before we go into this function, we should write some support functions and definitions which will help us a lot.

The Command/Status Port returns a bit mask referring to the status of a channel when read.

The Features/Error Port, which returns the most recent error upon read, has these possible bit masks

#define ATA_CMD_READ_PIO 0x20

#define ATA_CMD_READ_PIO_EXT 0x24

#define ATA_CMD_IDENTIFY_PACKET 0xA1

#define ATA_CMD_IDENTIFY 0xEC

#define ATAPI_CMD_READ 0xA8

#define ATAPI_CMD_EJECT 0x1B

ATA_CMD_IDENTIFY_PACKET and ATA_CMD_IDENTIFY return a buffer of 512 bytes called the identification space; the following definitions are used to read information from the identification space.

#define ATA_IDENT_DEVICETYPE 0

#define ATA_IDENT_CYLINDERS 2

#define ATA_IDENT_COMMANDSETS 164

#define ATA_IDENT_MAX_LBA_EXT 200

#define IDE_ATA 0x00

#define IDE_ATAPI 0x01

 

#define ATA_REG_DATA 0x00

#define ATA_REG_ERROR 0x01

#define ATA_REG_ALTSTATUS 0x0C

#define ATA_REG_DEVADDRESS 0x0D

The ALTSTATUS/CONTROL port returns the alternate status when read and controls a channel when written to.

* For the primary channel, ALTSTATUS/CONTROL port is BAR1 + 2.

* For the secondary channel, ALTSTATUS/CONTROL port is BAR3 + 2.

We can now say that each channel has 13 registers. For the primary channel, we use these values:

* Data Register: BAR0 + 0; // Read-Write

* Alternate Status Register: BAR1 + 2; // Read Only.

* Control Register: BAR1 + 2; // Write Only.

The map above is the same with the secondary channel, but it uses BAR2 and BAR3 instead of BAR0 and BAR1.

// Channels:

#define ATA_PRIMARY 0x00

#define ATA_SECONDARY 0x01

 

// Directions:

#define ATA_READ 0x00

#define ATA_WRITE 0x01

We have defined everything needed by the driver, now lets move to an important part. We said that

* BAR0 is the start of the I/O ports used by the primary channel.

* BAR4 is the start of 8 I/O ports controls the primary channel's Bus Master IDE.

* BAR4 + 8 is the Base of 8 I/O ports controls secondary channel's Bus Master IDE.

So we can make this global structure:

struct IDEChannelRegisters {

unsigned short base; // I/O Base.

unsigned char nIEN; // nIEN (No Interrupt);

} channels[2];

We also need a buffer to read the identification space into, we need a variable that indicates if an irq is invoked or not, and finally we need an array of 6 words [12 bytes] for ATAPI Drives:

unsigned char ide_buf[2048] = {0};

unsigned static char atapi_packet[12] = {0xA8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

We said the the IDE can contain up to 4 drives:

struct ide_device {

unsigned char Reserved; // 0 (Empty) or 1 (This Drive really exists).

unsigned char Model[41]; // Model in string.

} ide_devices[4];

When we read a register in a channel, like STATUS Register, it is easy to execute:

ide_read(channel, ATA_REG_STATUS);

 

return result;

}

We also need a function for writing to registers:

void ide_write(unsigned char channel, unsigned char reg, unsigned char data) {

if (reg > 0x07 && reg < 0x0C)

ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);

if (reg < 0x08)

else if (reg < 0x0C)

else if (reg < 0x0E)

else if (reg < 0x16)

if (reg > 0x07 && reg < 0x0C)

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);

}

To read the identification space, we should read the Data Register as a double word 128 times. We can then copy them to our buffer.

void ide_read_buffer(unsigned char channel, unsigned char reg, unsigned int buffer,

unsigned int quads) {

if (reg > 0x07 && reg < 0x0C)

ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);

}

When we send a command, we should wait for 400 nanosecond, then read the Status port. If the Busy bit is on, we should read the status port again until the Busy bit is 0; then we can read the results of the command. This operation is called "Polling". We can also use IRQs instead of polling.

 

After many commands, if the Device Fault bit is set, there is a failure; if DRQ is not set, there is an error. If the ERR bit is set, there is an error which is described in Error port.

unsigned char ide_polling(unsigned char channel, unsigned int advanced_check) {

 

 

}

If there is an error, we have a function which prints errors on screen:

unsigned char ide_print_error(unsigned int drive, unsigned char err) {

if (err == 0)

return err;

}

Now let's return to the initialization function:

void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,

unsigned int BAR4) {

// 1- Detect I/O Ports which interface IDE Controller:

channels[ATA_PRIMARY ].base = (BAR0 & 0xFFFFFFFC) + 0x1F0 * (!BAR0);

channels[ATA_SECONDARY].base = (BAR2 & 0xFFFFFFFC) + 0x170 * (!BAR2);

channels[ATA_PRIMARY ].bmide = (BAR4 & 0xFFFFFFFC) + 0; // Bus Master IDE

channels[ATA_SECONDARY].bmide = (BAR4 & 0xFFFFFFFC) + 8; // Bus Master IDE

// 2- Disable IRQs:

ide_write(ATA_PRIMARY , ATA_REG_CONTROL, 2);

ide_write(ATA_SECONDARY, ATA_REG_CONTROL, 2);

Now we need to check for drives which could be connected to each channel. We will select the master drive of each channel, and send the ATA_IDENTIFY command (which is supported by ATA Drives). If there's no error, there are values returned in registers which determine the type of Drive; if no drive is present, there will be strange values.

 

Notice that if bit 4 in HDDEVSEL is set to 1, we are selecting the slave drive, if set to 0, we are selecting the master drive.

// 3- Detect ATA-ATAPI Devices:

for (i = 0; i < 2; i++)

unsigned char ch = ide_read(i, ATA_REG_LBA2);

 

type = IDE_ATAPI;

else if (cl == 0x69 && ch == 0x96)

ide_devices[count].Channel = i;

ide_devices[count].Drive = j;

 

// (VII) Get Size:

if (ide_devices[count].CommandSets & (1 << 26))

// Device uses 48-Bit Addressing:

else

// Device uses CHS or 28-bit Addressing:

 

// (VIII) String indicates model of device (like Western Digital HDD and SONY DVD-RW...):

}

}

Now we're moving to a slightly more advanced part, it is to read and write from/to an ATA drive.

There is 3 ways of addressing a sector:

* LBA28: Accessing a sector by its 28-bit LBA address. All ATA drives should support this way of addressing, the problem with LBA28 Addressing is that it only allows access 128GB to be accessed, so if the disk is bigger than 128GB, it should support the LBA48 Feature Set.

* LBA48: Accessing a sector by its 48-bit LBA address. As we use integers in GCC, our maximum address in this tutorial is 32-bit long, which allows accessing a drive with a size of up to 2TB.

else

Reading the buffer may be done by polling or DMA.

DMA: After sending the command, you should wait for an IRQ, while you are waiting, Buffer is written directly to memory automatically.

 

 

We can conclude also this table:

/* ATA/ATAPI Read/Write Modes:

* ++++++++++++++++++++++++++++++++

* - Polling Status (+) // Suitable for Singletasking

*/

There is something needed to be expressed here, I have told before that Task-File is like that:

* Register 0: [Word] Data Register. (Read-Write).

* Register 7: [Byte] Command Register. (Write).

* Register 7: [Byte] Status Register. (Read).

So each register between 2 to 5 should be 8-bits long. Really each of them are 16-bits long.

* Register 2: [Bits 0-7] SECCOUNT0, [Bits 8-15] SECOUNT1

* Register 3: [Bits 0-7] LBA0, [Bits 8-15] LBA3

* Register 4: [Bits 0-7] LBA1, [Bits 8-15] LBA4

* Register 5: [Bits 0-7] LBA2, [Bits 8-15] LBA5

The word [(SECCOUNT1 << 8) | SECCOUNT0] expresses the number of sectors which can be read when you access by LBA48.

When you access in CHS or LBA28, SECCOUNT0 only expresses number of sectors.

* LBA0 makes up bits 0 : 7 of the LBA address when you read in LBA28 or LBA48; it can also be the sector number of CHS.

* LBA1 makes up bits 8 : 15 of the LBA address when you read in LBA28 or LBA48; it can also be the low byte of the cylinder number of CHS.

* LBA4 makes up bits 32 : 39 of the LBA48 address.

* LBA5 makes up bits 40 : 47 of LBA48 address.

Notice that the LBA0, 1 and 2 registers are 24 bits long in total, which is not enough for LBA28; the higher 4-bits can be written to the lower 4-bits of the HDDEVSEL register.

 

 

Lets go into the code:

unsigned char ide_ata_access(unsigned char direction, unsigned char drive, unsigned int lba,

unsigned char numsects, unsigned short selector, unsigned int edi) {

This function reads/writes sectors from ATA-Drive. If direction is 0 we are reading, else we are writing.

* drive is the drive number which can be from 0 to 3.

* numsects is the number of sectors to be read, it is a char, as reading more than 256 sector immediately may performance issues. If numsects is 0, the ATA controller will know that we want 256 sectors.

* selector is the segment selector to read from, or write to.

unsigned char lba_mode /* 0: CHS, 1:LBA28, 2: LBA48 */, dma /* 0: No DMA, 1: DMA */, cmd;

unsigned char lba_io[6];

unsigned short cyl, i;

unsigned char head, sect, err;

We don't need IRQs, so we should disable it to prevent problems from happening. We said before that if bit 1 of the Control Register (which is called nIEN bit), is set, no IRQs will be invoked from any drives on this channel, either master or slave.

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = (ide_irq_invoked = 0x0) + 0x02);

Now lets read the parameters:

// (I) Select one from LBA28, LBA48 or CHS;

if (lba >= 0x10000000) { // Sure Drive should support LBA in this case, or you are

head = (lba + 1 - sect) % (16 * 63) / (63); // Head number is written to HDDEVSEL lower 4-bits.

}

Now we are going to choose the way of reading the buffer [PIO or DMA]:

// (II) See if drive supports DMA or not;

dma = 0; // We don't support DMA

// (III) Wait if the drive is busy;

The HDDDEVSEL register now looks like this:

* Bit 4: Slave Bit. (0: Selecting Master Drive, 1: Selecting Slave Drive).

* Bit 5: Obsolete and isn't used, but should be set.

* Bit 6: LBA (0: CHS, 1: LBA).

* Bit 7: Obsolete and isn't used, but should be set.

Lets write all these information to the register, while the obsolete bits are set (0xA0):

// (IV) Select Drive from the controller;

if (lba_mode == 0)

else

ide_write(channel, ATA_REG_HDDEVSEL, 0xE0 | (slavebit << 4) | head); // Drive & LBA

Let's write the parameters to registers:

// (V) Write Parameters;

if (lba_mode == 2) {

ide_write(channel, ATA_REG_LBA1, lba_io[1]);

ide_write(channel, ATA_REG_LBA2, lba_io[2]);

 

Now, we have a great set of commands described in ATA/ATAPI-8 Specification, we should choose the suitable command to execute:

// (VI) Select the command and send it;

// Routine that is followed:

// If (!DMA & LBA28) DO_PIO_LBA;

// If (!DMA & !LBA#) DO_PIO_CHS;

There isn't a command for doing CHS with DMA.

if (lba_mode == 0 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;

if (lba_mode == 1 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;

if (lba_mode == 2 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA_EXT;

ide_write(channel, ATA_REG_COMMAND, cmd); // Send the Command.

This ATA_CMD_READ_PIO command is used for reading in LBA28 or CHS, and the IDE controller refers to bit 6 of the HDDEVSEL register to find out the mode of reading (LBA or CHS).

 

 

Notice that after writing, we should execute the CACHE FLUSH command, and we should poll after it, but without checking for errors.

if (dma)

if (direction == 0);

return 0; // Easy, isn't it?

}

 

 

void ide_wait_irq() {

while (!ide_irq_invoked)

ide_irq_invoked = 0;

}

void ide_irq() {

ide_irq_invoked = 1;

}

unsigned char ide_atapi_read(unsigned char drive, unsigned int lba, unsigned char numsects,

unsigned short selector, unsigned int edi) {

* drive is the drive number, which is from 0 to 3.

* lba is the LBA address.

* selector is the Segment Selector.

* edi is the offset in the selector.

Let's read the parameters of the drive:

unsigned int channel = ide_devices[drive].Channel;

unsigned int slavebit = ide_devices[drive].Drive;

unsigned int bus = channels[channel].Base;

unsigned char err;

int i;

We need IRQs:

// Enable IRQs:

ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = ide_irq_invoked = 0x0);

Let's setup the SCSI Packet, which is 6 words (12 bytes) long:

// (I): Setup SCSI Packet:

// ------------------------------------------------------------------

atapi_packet[10] = 0x0;

atapi_packet[11] = 0x0;

Now we should select the drive:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_HDDEVSEL, slavebit << 4);

400 nanoseconds delay after this select is a good idea:

// (III): Delay 400 nanoseconds for select to complete:

// ------------------------------------------------------------------

for(int i = 0; i < 4; i++)

ide_read(channel, ATA_REG_ALTSTATUS); // Reading the Alternate Status port wastes 100ns.

// (IV): Inform the Controller that we use PIO mode:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_FEATURES, 0); // PIO mode.

Tell the controller the size of the buffer

// (V): Tell the Controller the size of buffer:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_LBA1, (words * 2) & 0xFF); // Lower Byte of Sector Size.

ide_write(channel, ATA_REG_LBA2, (words * 2) >> 8); // Upper Byte of Sector Size.

// (VI): Send the Packet Command:

// ------------------------------------------------------------------

ide_write(channel, ATA_REG_COMMAND, ATA_CMD_PACKET); // Send the Command.

 

// ------------------------------------------------------------------

if (err = ide_polling(channel, 1)) return err; // Polling and return if error.

 

// (VIII): Sending the packet data:

// ------------------------------------------------------------------

asm("rep outsw" : : "c"(6), "d"(bus), "S"(atapi_packet)); // Send Packet Data

// (IX): Receiving Data:

// ------------------------------------------------------------------

for (i = 0; i < numsects; i++) {

ide_wait_irq(); // Wait for an IRQ.

asm("pushw %es");

asm("mov %%ax, %%es"::"a"(selector));

asm("rep insw"::"c"(words), "d"(bus), "D"(edi));// Receive Data.

asm("popw %es");

}

// (X): Waiting for an IRQ:

// ------------------------------------------------------------------

// (XI): Waiting for BSY & DRQ to clear:

// ------------------------------------------------------------------

 

return 0; // Easy, ... Isn't it?

}

void ide_read_sectors(unsigned char drive, unsigned char numsects, unsigned int lba,

unsigned short es, unsigned int edi) {

// 1: Check if the drive presents:

// ==================================

 

// 2: Check if inputs are valid:

// ==================================

package[0] = 0x2; // Seeking to invalid position.

 

else {

unsigned char err;

err = ide_ata_access(ATA_READ, drive, lba, numsects, es, edi);

for (i = 0; i < numsects; i++)

err = ide_atapi_read(drive, lba + i, 1, es, edi + (i*2048));

}

}

void ide_write_sectors(unsigned char drive, unsigned char numsects, unsigned int lba,

unsigned short es, unsigned int edi) {

// 1: Check if the drive presents:

// ==================================

// 2: Check if inputs are valid:

// ==================================

package[0] = 0x2; // Seeking to invalid position.

// 3: Read in PIO Mode through Polling & IRQs:

else {

unsigned char err;

err = ide_ata_access(ATA_WRITE, drive, lba, numsects, es, edi);

err = 4; // Write-Protected.

package[0] = ide_print_error(drive, err);

}

}

void ide_atapi_eject(unsigned char drive) {

unsigned int words = 2048 / 2; // Sector Size in Words.

unsigned char err = 0;

// 1: Check if the drive presents:

// ==================================

// 2: Check if drive isn't ATAPI:

// ==================================

// 3: Eject ATAPI Driver:

// ============================================

// (II): Select the Drive:

// ------------------------------------------------------------------

 

// (III): Delay 400 nanosecond for select to complete:

// ------------------------------------------------------------------

 

// (IV): Send the Packet Command:

// (V): Waiting for the driver to finish or invoke an error:

// ------------------------------------------------------------------

 

// (VI): Sending the packet data:

}

package[0] = ide_print_error(drive, err); // Return;

}

}

[[Category:ATA]]