PCI IDE Controller: Difference between revisions
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{{Disputed|Talk:IDE}}
IDE is a keyword which refers to the electrical specification of the cables which connect ATA drives (like hard drives) to another device. The drives use the ATA (Advanced Technology Attachment) interface. An IDE cable also can terminate at an IDE card connected to PCI.
[[ATAPI]] is an extension to ATA
== Parallel/Serial ATA/ATAPI ==
IDE can connect up to 4 drives. Each drive can be one of the following:
* ATA (Serial): Used for most modern hard drives.
* ATA (Parallel): Commonly used for hard drives.
* ATAPI (Serial): Used for most modern optical drives.
* ATAPI (Parallel): Commonly used for optical drives.
Accessing an ATA/PATA drive works the same way as accessing a SATA drive. This also implicitly states that accessing a PATAPI ODD is the same as accessing a SATAPI ODD. An IDE driver does not need to know whether a drive is parallel or serial, it only has to know whether it's using ATA or ATAPI.
== IDE Interface ==
If you open your case up and take a look at your motherboard, you will most likely see one or two (or possibly more) of the slots.
The white and green ports are IDE ports, also known as ''channels''. In this example there are both primary and secondary IDE channels which only PATA can be connected to; this means that it only supports PATA/PATAPI drives.
Each port can have a PATA cable connected to it. One master drive, or two drives (master and slave), can be connected to one PATA cable. So that leaves us with the following possibilities:
* Primary Master Drive.
* Primary Slave Drive.
* Secondary Master Drive.
* Secondary Slave Drive.
Each
== Serial IDE ==
Almost every modern (this article is probably written in early 2010 so it assumes motherboards still have ide/ahci modes) motherboard has a Serial IDE channel which allows [[SATA]] and SATAPI Drives to be connected to it. There are 4 Serial IDE Ports. Each port is connected to a drive with a SATA Cable. Basically you can only have one drive connected to the Serial IDE port. Each pair of ports (every 2 ports) form one channel.
Serial IDE also has a few possibilities:
* Primary Master, also called SATA1.
* Primary Slave, also called SATA2.
* Secondary Master, also called SATA3.
* Secondary Slave, also called SATA4.
== Detecting a PCI IDE Controller ==
Each IDE controller appears as a device on the [[PCI]] bus and can be identified by reading the configuration space. If the class code is 0x01 (Mass Storage Controller) and the subclass code is 0x01 (IDE), the device is an IDE controller. The programming interface byte(Prog If) determines how you'll access it.
* Bit 0: When set, the primary channel is in PCI native mode. When clear, the primary channel is in compatibility mode (ports 0x1F0-0x1F7, 0x3F6, IRQ14).
* Bit 1: When set, you can modify bit 0 to switch between PCI native and compatibility mode. When clear, you cannot modify bit 0.
* Bit 2: When set, the secondary channel is in PCI native mode. When clear, the secondary channel is in compatibility mode (ports 0x170-0x177, 0x376, IRQ15).
* Bit 3: When set, you can modify bit 2 to switch between PCI native and compatibility mode. When clear, you cannot modify bit 2.
* Bit 7: When set, this is a bus master IDE controller. When clear, this controller doesn't support DMA.
If you want to access an IDE channel in PCI native mode or use the bus master function, you must additionally read the BARs to find which I/O ports to use.
* BAR0: Base address of primary channel in PCI native mode (8 ports)
* BAR1: Base address of primary channel control port in PCI native mode (4 ports)
* BAR2: Base address of secondary channel in PCI native mode (8 ports)
* BAR3: Base address of secondary channel control port in PCI native mode (4 ports)
* BAR4: Bus master IDE (16 ports, 8 for each channel)
Note that BAR1 and BAR3 specify 4 ports, but only the port at offset 2 is used. Offsets 0, 1, and 3 should not be accessed.
If either IDE channel is in PCI native mode, you must also read the interrupt line or interrupt pin register to determine which interrupt to use. If both channels are in PCI native mode, they'll both share the same interrupt. The interrupt line field is only valid when using the [[8259 PIC|PIC]].
== Detecting IDE Drives ==
To initialise the IDE driver, we call ide_initialise:
<syntaxhighlight lang="c">
void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,
unsigned int BAR4) {
</syntaxhighlight>
If you only want to support the parallel IDE, you can use these parameters:
<syntaxhighlight lang="c">
ide_initialize(0x1F0, 0x3F6, 0x170, 0x376, 0x000);
</syntaxhighlight>
We can assume that BAR4 is 0x0 because we are not going to use it yet.
We will return to ide_initialize
=== Status ===
The Command/Status Port returns a bit mask referring to the status of a channel when read.
<
#define ATA_SR_BSY
#define ATA_SR_DRDY
#define ATA_SR_DF
#define ATA_SR_DSC
#define ATA_SR_DRQ
#define ATA_SR_CORR
#define ATA_SR_IDX
#define ATA_SR_ERR
</syntaxhighlight>
=== Errors ===
The Features/Error Port, which returns the most recent error upon read, has these possible bit masks
<syntaxhighlight lang="c">
#define ATA_ER_BBK 0x80 // Bad block
#define ATA_ER_UNC
#define ATA_ER_MC
#define ATA_ER_IDNF
#define ATA_ER_MCR
#define ATA_ER_ABRT
#define ATA_ER_TK0NF
#define ATA_ER_AMNF
</syntaxhighlight>
=== Commands ===
When you write to the Command/Status port, you are executing one of the commands below.
<syntaxhighlight lang="c">
#define ATA_CMD_READ_PIO 0x20
#define ATA_CMD_READ_PIO_EXT 0x24
#define ATA_CMD_READ_DMA 0xC8
#define ATA_CMD_READ_DMA_EXT
#define ATA_CMD_WRITE_PIO
#define ATA_CMD_WRITE_PIO_EXT
#define ATA_CMD_WRITE_DMA
#define ATA_CMD_WRITE_DMA_EXT
#define ATA_CMD_CACHE_FLUSH
#define ATA_CMD_CACHE_FLUSH_EXT 0xEA
#define ATA_CMD_PACKET
#define ATA_CMD_IDENTIFY_PACKET 0xA1
#define ATA_CMD_IDENTIFY
</syntaxhighlight>
The commands below are for ATAPI devices, which will be understood soon.
<syntaxhighlight lang="c">
#define ATAPI_CMD_READ 0xA8
#define ATAPI_CMD_EJECT 0x1B
</syntaxhighlight>
ATA_CMD_IDENTIFY_PACKET and ATA_CMD_IDENTIFY return a buffer of 512 bytes called the identification space; the following definitions are used to read information from the identification space.
<syntaxhighlight lang="c">
#define ATA_IDENT_DEVICETYPE 0
#define ATA_IDENT_CYLINDERS 2
#define ATA_IDENT_HEADS 6
#define ATA_IDENT_SECTORS 12
#define ATA_IDENT_SERIAL
#define ATA_IDENT_MODEL
#define ATA_IDENT_CAPABILITIES 98
#define ATA_IDENT_FIELDVALID 106
#define ATA_IDENT_MAX_LBA
#define ATA_IDENT_COMMANDSETS 164
#define ATA_IDENT_MAX_LBA_EXT 200
</syntaxhighlight>
When you select a drive, you should specify the interface type and whether it is the master or slave:
<syntaxhighlight lang="c">
#define IDE_ATA
#define IDE_ATAPI 0x01
#define ATA_MASTER 0x00
#define ATA_SLAVE 0x01
</syntaxhighlight>
Task File is a range of 8 ports which are offsets from BAR0 (primary channel) and/or BAR2 (secondary channel). To exemplify:
* BAR0 + 0 is first port.
* BAR0 + 1 is second port.
* BAR0 +
<syntaxhighlight lang="c">
#define ATA_REG_DATA 0x00
#define ATA_REG_ERROR 0x01
#define ATA_REG_FEATURES 0x01
#define ATA_REG_SECCOUNT0 0x02
#define ATA_REG_LBA0 0x03
#define ATA_REG_LBA1 0x04
#define ATA_REG_LBA2 0x05
#define ATA_REG_HDDEVSEL 0x06
#define ATA_REG_COMMAND 0x07
#define ATA_REG_STATUS 0x07
#define ATA_REG_SECCOUNT1 0x08
#define ATA_REG_LBA3 0x09
#define ATA_REG_LBA4 0x0A
#define ATA_REG_LBA5 0x0B
#define ATA_REG_CONTROL 0x0C
#define ATA_REG_ALTSTATUS 0x0C
#define ATA_REG_DEVADDRESS 0x0D
</syntaxhighlight>
The ALTSTATUS/CONTROL port returns the alternate status when read and controls a channel when written to.
* For the primary channel, ALTSTATUS/CONTROL port is BAR1 + 2.
* For the secondary channel, ALTSTATUS/CONTROL port is BAR3 + 2.
We can now say that each channel has 13 registers. For the primary channel, we use these values:
*
*
*
* SECCOUNT0: BAR0 + 2; // Read-Write
* LBA0: BAR0 + 3; // Read-Write
* LBA1: BAR0 + 4; // Read-Write
* LBA2: BAR0 + 5; // Read-Write
* HDDEVSEL: BAR0 + 6; // Read-Write, used to select a drive in the channel.
* Command Register: BAR0 + 7; // Write Only.
* Status Register: BAR0 + 7; // Read Only.
* Alternate Status Register: BAR1 + 2; // Read Only.
* Control Register: BAR1 + 2; // Write Only.
* DEVADDRESS: BAR1 + 3; // I don't know what is the benefit from this register.
The map above is the same with the secondary channel, but it uses BAR2 and BAR3 instead of BAR0 and BAR1.
<syntaxhighlight lang="c">
// Channels:
#define ATA_PRIMARY 0x00
#define ATA_SECONDARY 0x01
// Directions:
#define ATA_READ 0x00
#define ATA_WRITE 0x01
</syntaxhighlight>
We have defined everything needed by the driver, now lets move to an important part. We said that
* BAR0 is the start of the I/O ports used by the primary channel.
*
*
*
*
* BAR4 + 8 is the Base of 8 I/O
So we can make this global structure:
<syntaxhighlight lang="c">
struct IDEChannelRegisters {
unsigned short base; // I/O Base.
unsigned short ctrl; // Control Base
Line 276 ⟶ 190:
unsigned char nIEN; // nIEN (No Interrupt);
} channels[2];
</syntaxhighlight>
We also need a buffer to read the identification space into, we need a variable that indicates if an irq is invoked or not, and finally we need an array of 6 words [12 bytes] for ATAPI Drives:
<syntaxhighlight lang="c">
unsigned char ide_buf[2048] = {0};
volatile unsigned static char ide_irq_invoked = 0;
unsigned static char atapi_packet[12] = {0xA8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
</syntaxhighlight>
We said the the IDE can contain up to 4 drives:
<syntaxhighlight lang="c">
struct ide_device {
unsigned char
unsigned char
unsigned char
unsigned short
unsigned short
unsigned short
unsigned int
unsigned int
unsigned char
} ide_devices[4];
</syntaxhighlight>
When we read a register in a channel, like STATUS Register, it is easy to execute:
<syntaxhighlight lang="c">
ide_read(channel, ATA_REG_STATUS);
unsigned char ide_read(unsigned char channel, unsigned char reg) {
unsigned char result;
if
if (reg < 0x08)
else if
else if (reg < 0x0E)
result = inb(channels[channel].ctrl + reg - 0x0A);
else if (reg < 0x16)
result = inb(channels[channel].bmide + reg - 0x0E);
if (reg > 0x07 && reg < 0x0C)
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
return result;
}
</syntaxhighlight>
We also need a function for writing to registers:
<syntaxhighlight lang="c">
void ide_write(unsigned char channel, unsigned char reg, unsigned char data) {
if
if (reg < 0x08)
else if
outb(channels[channel].base + reg - 0x06, data);
else if (reg < 0x0E)
outb(channels[channel].ctrl + reg - 0x0A, data);
else if (reg < 0x16)
outb(channels[channel].bmide + reg - 0x0E, data);
if (reg > 0x07 && reg < 0x0C)
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
}
</syntaxhighlight>
To read the identification space, we should read the Data Register as a double word 128 times. We can then copy them to our buffer.
<syntaxhighlight lang="c">
void ide_read_buffer(unsigned char channel, unsigned char reg, unsigned int buffer,
unsigned int quads) {
/* WARNING: This code contains a serious bug. The inline assembly trashes ES and
* ESP for all of the code the compiler generates between the inline
* assembly blocks.
*/
if (reg > 0x07 && reg < 0x0C)
ide_write(channel, ATA_REG_CONTROL, 0x80 | channels[channel].nIEN);
asm("pushw %es; movw %ds, %ax; movw %ax, %es");
if
else if
else if (reg < 0x0E)
insl(channels[channel].ctrl + reg - 0x0A, buffer, quads);
else if (reg < 0x16)
insl(channels[channel].bmide + reg - 0x0E, buffer, quads);
asm("popw %es;");
if
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN);
}
</syntaxhighlight>
When we send a command, we should wait for 400 nanosecond, then read the Status port. If the Busy bit is on, we should read the status port again until the Busy bit is 0; then we can read the results of the command. This operation is called "Polling". We can also use IRQs instead of polling.
After many commands, if the Device Fault bit is set, there is a failure; if DRQ is not set, there is an error. If the ERR bit is set, there is an error which is described in Error port.
<syntaxhighlight lang="c">
unsigned char ide_polling(unsigned char channel, unsigned int advanced_check) {
// (I) Delay 400 nanosecond for BSY to be set:
// -------------------------------------------------
for(int i = 0; i < 4; i++)
ide_read(channel, ATA_REG_ALTSTATUS); // Reading the Alternate Status
// (II) Wait for BSY to be cleared:
// -------------------------------------------------
while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY)
; // Wait for BSY to be zero.
if (advanced_check) {
unsigned char state = ide_read(channel, ATA_REG_STATUS); // Read Status Register.
// (III) Check For Errors:
// -------------------------------------------------
if (state & ATA_SR_ERR)
return 2; // Error.
// (IV) Check If Device fault:
// -------------------------------------------------
if (state & ATA_SR_DF
return 1; // Device Fault.
// (V) Check DRQ:
// -------------------------------------------------
// BSY = 0; DF = 0; ERR = 0 so we should check for DRQ now.
if (
return 3; // DRQ should be set
}
Line 389 ⟶ 313:
}
</syntaxhighlight>
If there is an error, we have a function which prints errors on screen:
<syntaxhighlight lang="c">
unsigned char ide_print_error(unsigned int drive, unsigned char err) {
if (err == 0)
printk("
if (err == 1) {printk("- Device Fault\n "); err = 19;}
else if (err == 2) {
Line 413 ⟶ 335:
else if (err == 4) {printk("- Write Protected\n "); err = 8;}
printk("- [%s %s] %s\n",
(const char *[]){"Primary", "Secondary"}[ide_devices[drive].channel], // Use the channel as an index into the array
(const char *[]){"Master", "Slave"}[ide_devices[drive].drive], // Same as above, using the drive
ide_devices[drive].model);
return err;
}
</syntaxhighlight>
Now let's return to the initialization function:
<syntaxhighlight lang="c">
void ide_initialize(unsigned int BAR0, unsigned int BAR1, unsigned int BAR2, unsigned int BAR3,
unsigned int BAR4) {
Line 430 ⟶ 350:
// 1- Detect I/O Ports which interface IDE Controller:
channels[ATA_PRIMARY ].base = (BAR0 &
channels[ATA_PRIMARY ].ctrl = (BAR1 &
channels[ATA_SECONDARY].base = (BAR2 &
channels[ATA_SECONDARY].ctrl = (BAR3 &
channels[ATA_PRIMARY ].bmide = (BAR4 &
channels[ATA_SECONDARY].bmide = (BAR4 &
</syntaxhighlight>
Then we should disable IRQs in both channels by setting bit 1 (nIEN) in the Control port:
<syntaxhighlight lang="c">
// 2- Disable IRQs:
ide_write(ATA_PRIMARY , ATA_REG_CONTROL, 2);
ide_write(ATA_SECONDARY, ATA_REG_CONTROL, 2);
</syntaxhighlight>
Now we need to check for drives which could be connected to each channel. We will select the master drive of each channel, and send the ATA_IDENTIFY command (which is supported by ATA Drives). If there's no error, there are values returned in registers which determine the type of Drive; if no drive is present, there will be strange values.
Notice that if bit 4 in HDDEVSEL is set to 1, we are selecting the slave drive, if set to 0, we are selecting the master drive.
<syntaxhighlight lang="c">
// 3- Detect ATA-ATAPI Devices:
for (i = 0; i < 2; i++)
Line 457 ⟶ 372:
unsigned char err = 0, type = IDE_ATA, status;
ide_devices[count].
// (I) Select Drive:
ide_write(i, ATA_REG_HDDEVSEL, 0xA0 | (j << 4)); // Select Drive.
sleep(1); // Wait 1ms for drive select to work.
Line 469 ⟶ 384:
// (III) Polling:
if
while(1) {
status = ide_read(i, ATA_REG_STATUS);
if (
if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRQ)) break; // Everything is right.
}
Line 479 ⟶ 394:
// (IV) Probe for ATAPI Devices:
if (err != 0) {
unsigned char cl = ide_read(i, ATA_REG_LBA1);
unsigned char ch = ide_read(i, ATA_REG_LBA2);
if
else
type = IDE_ATAPI;
else
continue; // Unknown Type (may not be a device).
ide_write(i, ATA_REG_COMMAND, ATA_CMD_IDENTIFY_PACKET);
Line 495 ⟶ 413:
// (VI) Read Device Parameters:
ide_devices[count].
ide_devices[count].
ide_devices[count].
ide_devices[count].
ide_devices[count].
ide_devices[count].
ide_devices[count].
// (VII) Get Size:
if (ide_devices[count].
// Device uses 48-Bit Addressing:
ide_devices[count].
else
// Device uses CHS or 28-bit Addressing:
ide_devices[count].
// (VIII) String indicates model of device (like Western Digital HDD and SONY DVD-RW...):
for(k =
ide_devices[count].
ide_devices[count].
ide_devices[count].
count++;
Line 524 ⟶ 440:
// 4- Print Summary:
for (i = 0; i < 4; i++)
if (ide_devices[i].
printk(" Found %s Drive %dGB - %s\n",
(const char *[]){"ATA", "ATAPI"}[ide_devices[i].
ide_devices[i].
ide_devices[i].
}
}
</syntaxhighlight>
== Read/Write From ATA Drive ==
Now we're moving to a slightly more advanced part, it is to read and write from/to an ATA drive.
There is 3 ways of addressing a sector:
* CHS (Cylinder-Head-Sector): an old way of addressing sectors in ATA drives,
* LBA28: Accessing a sector by its
* LBA48: Accessing a sector by its
So we can conclude an algorithm to determine which type of Addressing we are going to use:
<pre>
if (No LBA support)
Use CHS.
else if (the LBA Sector Address > 0x0FFFFFFF)
else
</pre>
Reading the buffer may be done by polling or DMA.
PIO: After sending the command
DMA: After sending the command, you should wait for an IRQ, while you are waiting, Buffer is written directly to memory automatically.
We are going to use PIO as it
We can conclude also this table:
<syntaxhighlight lang="c">
/* ATA/ATAPI Read/Write Modes:
* ++++++++++++++++++++++++++++++++
* Addressing Modes:
* ================
* - LBA28 Mode.
* - LBA48 Mode.
* - CHS. (+)
* Reading Modes:
Line 576 ⟶ 487:
* ================
* - IRQs
* - Polling Status
*/
</syntaxhighlight>
There is something needed to be expressed here, I have told before that Task-File is like that:
* Register 0: [Word] Data Register.
* Register 1: [Byte] Error Register.
* Register 1: [Byte] Features Register.
* Register 2: [Byte] SECCOUNT0 Register.
* Register 3: [Byte] LBA0 Register.
* Register 4: [Byte] LBA1 Register.
* Register 5: [Byte] LBA2 Register.
* Register 6: [Byte] HDDEVSEL Register.
* Register 7: [Byte] Command Register.
* Register 7: [Byte] Status Register.
So each register between 2 to 5 should be 8-bits long. Really each of them are 16-bits long.
* Register 2: [Bits 0-7] SECCOUNT0, [Bits 8-15] SECOUNT1
* Register 3: [Bits 0-7] LBA0, [Bits 8-15] LBA3
* Register 4: [Bits 0-7] LBA1, [Bits 8-15] LBA4
* Register 5: [Bits 0-7] LBA2, [Bits 8-15] LBA5
The word [(SECCOUNT1 << 8) | SECCOUNT0] expresses the number of sectors which can be read when you access by LBA48.
When you access in CHS or LBA28, SECCOUNT0 only expresses number of sectors.
* LBA0 makes up bits 0 : 7 of the LBA address when you read in LBA28 or LBA48; it can also be the sector number of CHS.
* LBA1 makes up bits 8 : 15 of the LBA address when you read in LBA28 or LBA48; it can also be the low byte of the cylinder number of CHS.
* LBA2 makes up bits 16 : 23 of the LBA address when you read in LBA28 or LBA48; it can also be the high byte of the cylinder number of CHS.
* LBA3 makes up bits 24 : 31 of the LBA48 address.
* LBA4 makes up bits 32 : 39 of the LBA48 address.
* LBA5 makes up bits 40 : 47 of LBA48 address.
Notice that the LBA0, 1 and 2 registers are 24 bits long in total, which is not enough for LBA28; the higher 4-bits can be written to the lower 4-bits of the HDDEVSEL register.
Also notice that if bit 6 of this register is set, we are going to use LBA, if not, we are going to use CHS. There is a mode which is called extended CHS.
Lets go into the code:
<syntaxhighlight lang="c">
unsigned char ide_ata_access(unsigned char direction, unsigned char drive, unsigned int lba,
</syntaxhighlight>
This function reads/writes sectors from ATA-Drive. If direction is 0 we are reading, else we are writing.
* drive is the drive number which can be from 0 to 3.
* lba is the LBA address which allows us to access disks up to 2TB.
* numsects is the number of sectors to be read, it is a char, as reading more than 256 sector immediately may performance issues. If numsects is 0, the ATA controller will know that we want 256 sectors.
*
* edi is the offset in that segment. (the memory address for the data buffer)
<syntaxhighlight lang="c">
unsigned char lba_mode /* 0: CHS, 1:LBA28, 2: LBA48 */, dma /* 0: No DMA, 1: DMA */, cmd;
unsigned char lba_io[6];
unsigned int channel = ide_devices[drive].
unsigned int slavebit = ide_devices[drive].
unsigned int bus
unsigned int words = 256; //
unsigned short cyl, i
unsigned char head, sect, err;
</syntaxhighlight>
We don't need IRQs, so we should disable it to
<syntaxhighlight lang="c">
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = (ide_irq_invoked = 0x0) + 0x02);
</syntaxhighlight>
Now lets read the parameters:
<syntaxhighlight lang="c">
// (I) Select one from LBA28, LBA48 or CHS;
if (lba >= 0x10000000) { // Sure Drive should support LBA in this case, or you are
// giving a wrong LBA.
// LBA48:
lba_mode = 2;
lba_io[0] = (lba & 0x000000FF) >> 0;
lba_io[1] = (lba & 0x0000FF00) >> 8;
lba_io[2] = (lba & 0x00FF0000) >> 16;
lba_io[3] = (lba & 0xFF000000) >> 24;
lba_io[4] = 0; //
lba_io[5] = 0; //
head = 0; // Lower 4-bits of HDDEVSEL are not used here.
} else if (ide_devices[drive].
// LBA28:
lba_mode = 1;
lba_io[0] = (lba & 0x00000FF) >> 0;
lba_io[1] = (lba & 0x000FF00) >> 8;
lba_io[2] = (lba & 0x0FF0000) >> 16;
lba_io[3] = 0; // These Registers are not used here.
lba_io[4] = 0; // These Registers are not used here.
lba_io[5] = 0; // These Registers are not used here.
head = (lba & 0xF000000) >> 24;
} else {
// CHS:
lba_mode = 0;
sect = (lba % 63) + 1;
cyl = (lba + 1 - sect) / (16 * 63);
lba_io[0] = sect;
lba_io[1] = (cyl >> 0) & 0xFF;
lba_io[2] = (cyl >> 8) & 0xFF;
lba_io[3] = 0;
lba_io[4] = 0;
lba_io[5] = 0;
head = (lba + 1 - sect) % (16 * 63) / (63); // Head number is written to HDDEVSEL lower 4-bits.
}
</syntaxhighlight>
Now we are going to choose the way of reading the buffer [PIO or DMA]:
<syntaxhighlight lang="c">
// (II) See if drive supports DMA or not;
dma = 0; //
</syntaxhighlight>
Lets poll the Status port while the channel is busy:
<syntaxhighlight lang="c">
// (III) Wait if the drive is busy;
while (ide_read(channel, ATA_REG_STATUS) & ATA_SR_BSY)
} // Wait if busy.
</syntaxhighlight>
The HDDDEVSEL register now looks like this:
* Bits 0
* Bit 4: Slave Bit. (0: Selecting Master Drive, 1: Selecting Slave Drive).
* Bit 5:
* Bit 6: LBA (0: CHS, 1: LBA).
* Bit 7:
Lets write all these information to the register, while the obsolete bits are set (0xA0):
<syntaxhighlight lang="c">
// (IV) Select Drive from the controller;
if (lba_mode == 0)
else
ide_write(channel, ATA_REG_HDDEVSEL, 0xE0 | (slavebit << 4) | head); // Drive & LBA
</syntaxhighlight>
Let's write the parameters to registers:
<syntaxhighlight lang="c">
// (V) Write Parameters;
if (lba_mode == 2) {
Line 728 ⟶ 620:
ide_write(channel, ATA_REG_LBA1, lba_io[1]);
ide_write(channel, ATA_REG_LBA2, lba_io[2]);
</syntaxhighlight>
If you are using LBA48 and want to write to the LBA0 and LBA3 registers, you should write LBA3 to Register 3, then write LBA0 to Register 3. ide_write function makes it quite simple, refer to the function and you will fully understand the code.
Now, we have a great set of commands described in ATA/ATAPI-8 Specification, we should choose the suitable command to execute:
<syntaxhighlight lang="c">
// (VI) Select the command and send it;
// Routine that is followed:
Line 743 ⟶ 633:
// If (!DMA & LBA28) DO_PIO_LBA;
// If (!DMA & !LBA#) DO_PIO_CHS;
</syntaxhighlight>
There isn't a command for doing CHS with DMA.
<syntaxhighlight lang="c">
if (lba_mode == 0 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;
if (lba_mode == 1 && dma == 0 && direction == 0) cmd = ATA_CMD_READ_PIO;
Line 761 ⟶ 649:
if (lba_mode == 2 && dma == 1 && direction == 1) cmd = ATA_CMD_WRITE_DMA_EXT;
ide_write(channel, ATA_REG_COMMAND, cmd); // Send the Command.
</syntaxhighlight>
This ATA_CMD_READ_PIO command is used for reading in LBA28 or CHS, and the IDE controller refers to bit 6 of the HDDEVSEL register to find out the mode of reading (LBA or CHS).
After sending the command, we should poll, then we read/write a sector, then we should poll, then we read/write a sector, until we read/write all sectors needed, if an error has happened, the function will return a specific error code.
Notice that after writing, we should execute the CACHE FLUSH command, and we should poll after it, but without checking for errors.
<syntaxhighlight lang="c">
if (dma)
if (direction == 0);
// DMA Read.
else;
// DMA Write.
else
if (direction == 0)
// PIO Read.
for (i = 0; i < numsects; i++) {
if (err = ide_polling(channel, 1))
return err; // Polling, set error and exit if there is.
asm("pushw %es");
asm("mov %%ax, %%es" : : "a"(selector));
asm("rep insw" : : "c"(words), "d"(bus), "D"(edi)); // Receive Data.
asm("popw %es");
edi += (words*2);
} else {
// PIO Write.
for (i = 0; i < numsects; i++) {
ide_polling(channel, 0); // Polling.
asm("pushw %ds");
asm("mov %%ax, %%ds"::"a"(selector));
asm("rep outsw"::"c"(words), "d"(bus), "S"(edi)); // Send Data
asm("popw %ds");
edi += (words*2);
}
ide_write(channel, ATA_REG_COMMAND, (char []) { ATA_CMD_CACHE_FLUSH,
ATA_CMD_CACHE_FLUSH,
ATA_CMD_CACHE_FLUSH_EXT}[lba_mode]);
ide_polling(channel, 0); // Polling.
}
return 0; // Easy,
}
</syntaxhighlight>
== Reading from an ATAPI Drive ==
Let's move to an easier part - reading from an ATAPI drive. I will not make the function that writes to an ATAPI drive, because writing to it is very complex and is outside of the scope of this tutorial.
An ATAPI drive is different from an ATA drive, as it uses the SCSI command set instead of the ATA command set. Parameters are sent as packets, therefore it's called the ATA Packet Interface [ATAPI].
Notice also that ATAPI drives always use IRQs and you can't disable them. We should create a function that waits for an IRQ:
<syntaxhighlight lang="c">
void ide_wait_irq() {
while (!ide_irq_invoked)
;
ide_irq_invoked = 0;
}
</syntaxhighlight>
When an IRQ happens, the following function should be executed by ISR:
<syntaxhighlight lang="c">
void ide_irq() {
ide_irq_invoked = 1;
}
</syntaxhighlight>
ide_wait_irq will go into a while loop, which waits for the variable ide_irq_invoked to be set, then clears it.
<syntaxhighlight lang="c">
unsigned char ide_atapi_read(unsigned char drive, unsigned int lba, unsigned char numsects,
unsigned short selector, unsigned int edi) {
</syntaxhighlight>
* drive is the drive number, which is from 0 to 3.
*
* numsects is the number of sectors. It should always be 1, and if you want to read more than one sector, re-execute this function with th updated LBA address.
* selector is the Segment Selector.
* edi is the offset in the selector.
Let's read the parameters of the drive:
<syntaxhighlight lang="c">
unsigned int channel = ide_devices[drive].Channel;
unsigned int
unsigned int
unsigned int
unsigned char err;
</syntaxhighlight>
We need IRQs:
<syntaxhighlight lang="c">
// Enable IRQs:
ide_write(channel, ATA_REG_CONTROL, channels[channel].nIEN = ide_irq_invoked = 0x0);
</syntaxhighlight>
Let's setup the SCSI Packet, which is 6 words (12 bytes) long:
<syntaxhighlight lang="c">
// (I): Setup SCSI Packet:
// ------------------------------------------------------------------
atapi_packet[ 0] = ATAPI_CMD_READ;
atapi_packet[ 1] = 0x0;
atapi_packet[ 2] = (lba >> 24) & 0xFF;
atapi_packet[ 3] = (lba >> 16) & 0xFF;
atapi_packet[ 4] = (lba >> 8) & 0xFF;
atapi_packet[ 5] = (lba >> 0) & 0xFF;
atapi_packet[ 6] = 0x0;
atapi_packet[ 7] = 0x0;
Line 873 ⟶ 750:
atapi_packet[10] = 0x0;
atapi_packet[11] = 0x0;
</syntaxhighlight>
Now we should select the drive:
<syntaxhighlight lang="c">
// (II): Select the drive:
// ------------------------------------------------------------------
ide_write(channel, ATA_REG_HDDEVSEL, slavebit << 4);
</syntaxhighlight>
400 nanoseconds delay after this select is a good idea:
<syntaxhighlight lang="c">
// (III): Delay 400 nanoseconds for select to complete:
// ------------------------------------------------------------------
for(int i = 0; i < 4; i++)
ide_read(channel, ATA_REG_ALTSTATUS); // Reading the Alternate Status
</syntaxhighlight>
<syntaxhighlight lang="c">
// (IV): Inform the Controller that we use PIO mode:
// ------------------------------------------------------------------
ide_write(channel, ATA_REG_FEATURES, 0); // PIO mode.
</syntaxhighlight>
Tell the controller the size of the buffer
<syntaxhighlight lang="c">
// (V): Tell the Controller the size of buffer:
// ------------------------------------------------------------------
ide_write(channel, ATA_REG_LBA1, (words * 2) & 0xFF); // Lower Byte of Sector Size.
ide_write(channel, ATA_REG_LBA2, (words * 2) >> 8); // Upper Byte of Sector Size.
</syntaxhighlight>
Now that we want to send the packet, we should first send the command "Packet":
<syntaxhighlight lang="c">
// (VI): Send the Packet Command:
// ------------------------------------------------------------------
ide_write(channel, ATA_REG_COMMAND, ATA_CMD_PACKET); // Send the Command.
// (VII): Waiting for the driver to finish or return an error code:
// ------------------------------------------------------------------
if (err = ide_polling(channel, 1)) return err; // Polling and return if error.
// (VIII): Sending the packet data:
// ------------------------------------------------------------------
asm("rep outsw" : : "c"(6), "d"(bus), "S"(atapi_packet)); // Send Packet Data
</syntaxhighlight>
Here we cannot poll. We should wait for an IRQ, then read the sectors. These two operations should be repeated for each sector.
<syntaxhighlight lang="c">
// (IX): Receiving Data:
// ------------------------------------------------------------------
for (i = 0; i < numsects; i++) {
ide_wait_irq(); // Wait for an IRQ.
if (err = ide_polling(channel, 1))
return err; // Polling and return if error.
asm("pushw %es");
asm("mov %%ax, %%es"::"a"(selector));
asm("rep insw"::"c"(words), "d"(bus), "D"(edi));// Receive Data.
asm("popw %es");
edi += (words * 2);
}
</syntaxhighlight>
Now we should wait for an IRQ and poll until the Busy and DRQ bits are clear:
<syntaxhighlight lang="c">
// (X): Waiting for an IRQ:
// ------------------------------------------------------------------
Line 954 ⟶ 813:
// (XI): Waiting for BSY & DRQ to clear:
// ------------------------------------------------------------------
while (ide_read(channel, ATA_REG_STATUS) & (ATA_SR_BSY | ATA_SR_DRQ))
;
return 0; // Easy, ... Isn't it?
}
</syntaxhighlight>
== Reading from an ATA/ATAPI Drive ==
<syntaxhighlight lang="c">
void ide_read_sectors(unsigned char drive, unsigned char numsects, unsigned int lba,
// 1: Check if the drive presents:
// ==================================
if (drive > 3 || ide_devices[drive].
// 2: Check if inputs are valid:
// ==================================
else if (((lba + numsects) > ide_devices[drive].
package[0] = 0x2; // Seeking to invalid position.
Line 978 ⟶ 837:
else {
unsigned char err;
if (ide_devices[drive].
err = ide_ata_access(ATA_READ, drive, lba, numsects, es, edi);
else if (ide_devices[drive].
for (i = 0; i < numsects; i++)
err = ide_atapi_read(drive, lba + i, 1, es, edi + (i*2048));
Line 986 ⟶ 845:
}
}
// package[0] is an entry of an array
</syntaxhighlight>
== Writing to an ATA drive ==
<syntaxhighlight lang="c">
void ide_write_sectors(unsigned char drive, unsigned char numsects, unsigned int lba,
// 1: Check if the drive presents:
// ==================================
if (drive > 3 || ide_devices[drive].
package[0] = 0x1; // Drive Not Found!
// 2: Check if inputs are valid:
// ==================================
else if (((lba + numsects) > ide_devices[drive].
package[0] = 0x2; // Seeking to invalid position.
// 3: Read in PIO Mode through Polling & IRQs:
Line 1,005 ⟶ 864:
else {
unsigned char err;
if (ide_devices[drive].
err = ide_ata_access(ATA_WRITE, drive, lba, numsects, es, edi);
else if (ide_devices[drive].
err = 4; // Write-Protected.
package[0] = ide_print_error(drive, err);
}
}
</syntaxhighlight>
== Ejecting an ATAPI Drive ==
<syntaxhighlight lang="c">
void ide_atapi_eject(unsigned char drive) {
unsigned int channel = ide_devices[drive].
unsigned int slavebit = ide_devices[drive].
unsigned int bus = channels[channel].
unsigned int words = 2048 / 2; // Sector Size in Words.
unsigned char err = 0;
Line 1,026 ⟶ 884:
// 1: Check if the drive presents:
// ==================================
if (drive > 3 || ide_devices[drive].
package[0] = 0x1; // Drive Not Found!
// 2: Check if drive isn't ATAPI:
// ==================================
else if (ide_devices[drive].
package[0] = 20; // Command Aborted.
// 3: Eject ATAPI Driver:
// ============================================
Line 1,053 ⟶ 913:
// (II): Select the Drive:
// ------------------------------------------------------------------
ide_write(channel, ATA_REG_HDDEVSEL, slavebit << 4);
// (III): Delay 400 nanosecond for select to complete:
// ------------------------------------------------------------------
for(int i = 0; i < 4; i++)
ide_read(channel, ATA_REG_ALTSTATUS); // Reading Alternate Status Port wastes 100ns.
// (IV): Send the Packet Command:
Line 1,068 ⟶ 926:
// (V): Waiting for the driver to finish or invoke an error:
// ------------------------------------------------------------------
// (VI): Sending the packet data:
Line 1,079 ⟶ 937:
}
package[0] = ide_print_error(drive, err); // Return;
}
}
</syntaxhighlight>
When this method is invoked, the optical device on the given channel is ejected.
== See Also ==
=== Wiki Pages ===
* [[MBR_(x86)|Master Boot Record (x86)]]
* [[Partition_Table|Partition Table (x86)]]
==
* [http://www.osdev.org/phpBB2/viewtopic.php?t=12268 How to w/r harddisk in pmode? (ASM Code from Dex)]
* [http://www.osdev.org/phpBB2/viewtopic.php?t=
* [http://
=== External Links ===
* [http://www.t13.org T13] -- The group that creates the ATA standard
* [http://www.ata-atapi.com ATA-ATAPI] -- Public Domain C driver sources (including SATA, Busmatering DMA, ATAPI), fairly good.
* [http://
* [http://www.ranish.com/part/primer.htm Partitioning Primer] -- A .HTM file containing some information about partitioning.
* [http://www.bswd.com/pciide.pdf PCI IDE Controller Specification] -- Specification containing information on "compatibility mode" and "PCI native mode" (and switching between them)
* [http://bswd.com/idems100.pdf Programming Interface for Bus Master IDE Controller] -- Bus Master IDE specification
[[Category:ATA]]
[[Category:Storage]]
[[de:AT Attachment]]
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