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PCI Express: Difference between revisions
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The PCI Express bus is a backwards compatible, high performance, general purpose I/O interconnect bus, and was designed for a range of computing platforms. One of the key improvements of PCI Express, over the [[PCI|PCI Local Bus]], is that it now uses a serial interface (compared to the parallel interface used by PCI). This improvement can be compared to the similiar serialization of the ATA interface.
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==PCI Express Link==
The PCI Express bus connects each device directly to the CPU and other system devices through a pair of high speed unidirectional differential links (transmit and recieve, respectively). These links operate at an effective rate of 2.5 GB/s and a single device may have multiple links. A single device may have x1, x2, x4, x8, x12, x16, or x32 links and can achieve a maximum bandwidth of 80 GB/s by utilizing x32 links.
==Extended Configuration Space==
The PCI Express bus extends the [[PCI#Configuration Space|Configuration Space]] from 256 bytes to 4096 bytes. This extended configuration space
However, the legacy configuration space for
===Changes from the PCI Configuration Space===
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| 11 || Discard Timer SERR# Enable: Does not apply to PCIe. Hardwired to 0.
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==Extended PCI Bus Numbering==
Older variations of PCI (e.g. "PCI Conventional") were limited to a maximum of 256 PCI bus segments. PCI Express extends this by introducing "PCI Segment Groups", where a system could (in theory) have up to 65536 PCI Segment Groups with 256 PCI bus segments per group, thereby allowing a single computer to have up to a maximum of 2<sup>24</sup> (16777216) PCI bus segments.
PCI Segment Groups are numbered, and in most systems there is only one PCI Segment Group (PCI Segment Group number 0). Note that legacy PCI configuration space access mechanism #1 (which still exists for backward compatibility) has no "PCI Segment Group" field and therefore can only be used to access the PCI configuration space for PCI Segment Group number 0. The [[#Enhanced Configuration Mechanism]] must be used to access the PCI configuration space for any devices in other PCI Segment Groups.
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For non-x86 systems the method varies, but usually systems provide themselves with a
To access a specific register within a device's PCI configuration space, you have to use the device's PCI Segment Group and bus to determine which memory mapped PCI configuration space area to use, and obtain the starting physical address and starting bus number for that memory mapped area. Once you have the correct starting physical address and starting bus number for that memory mapped area you would use the following formula to determine where the (4096-byte) area for a function's PCI configuration space is: <code>Physical_Address = MMIO_Starting_Physical_Address + (
Note that it may be a good idea to determine "physical address for this function's PCI configuration space" as part of PCI enumeration and store this physical address alongside any other information you're using to manage PCI devices and drivers (e.g. in your "device manager's" hierarchical tree of device info).
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Also note that for absolute maximums (with 65536 PCI segment groups and 256 bus segments per segment group), the amount of physical address space consumed by memory mapped PCI configuration space ranges would be (up to) 16 TiB (or 2<sup>44</sup> bytes); and ACPI's "MCFG" table may (in theory) be slightly larger than 256 MiB (a 16-byte entry for each individual PCI bus within each PCI segment group plus the 36-byte table header).
Accessing a specific device within the space can be as follows: <code>(((
Finding devices can be done [[PCI#Enumerating_PCI_Buses|the same as PCI]], with the difference that the kernel accesses a memory region rather than using CPU I/O.
==See Also==
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