PCI: Difference between revisions

 

 

The following field descriptions are common to all Header Types:

* '''Device ID:''' Identifies the particular device. Where valid IDs are allocated by the vendor.

* '''Latency Timer:''' Specifies the latency timer in units of PCI bus clocks.

* '''Cache Line Size:''' Specifies the system cache line size in 32-bit units. A device can limit the number of cacheline sizes it can support, if a unsupported value is written to this field, the device will behave as if a value of 0 was written.

 

This table is applicable if the Header Type is 00h. (Figure 2)

* '''Capabilities Pointer:''' Points (i.e. an offset into this function's configuration space) to a linked list of new capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1. The bottom two bits are reserved and should be masked before the Pointer is used to access the Configuration Space.

 

 

This table is applicable if the Header Type is 01h (PCI-to-PCI bridge) (Figure 3)

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Here is the layout of the Header Type register:

'''Header Type''' - 00h Standard Header - 01h PCI-to-PCI Bridge - 02h CardBus Bridge

 

 

Here is the layout of the BIST register:

 

'''Completion Code''' - Will return 0, after BIST execution, if the test completed successfully.

 

This table is applicable if the Header Type is 02h (PCI-to-CardBus bridge)

| colspan="4" | 16-bit PC Card legacy mode base address

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Here is the layout of the Command register:

'''I/O Space''' - If set to 1 the device can respond to I/O Space accesses; otherwise, the device's response is disabled.

 

 

Here is the layout of the Status register:

 

=== Base Address Registers ===

Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for port addresses. Typically, memory address BARs need to be located in physical ram while I/O space BARs can reside at any memory address (even beyond physical memory). To distinguish between them, you can check the value of the lowest bit. The following tables describe the two types of BARs: