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PCI: Difference between revisions
Explain "prefetchable"
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(→Configuration Space Access Mechanism #1: Source: Examples (NOT description) from http://faculty.chemeketa.edu/csekafet/ELT256/Adv_Chipset_AGp_DVO_PCI_CFG.pdf and even code from this wiki page. It has nothing to do with register number!) |
(Explain "prefetchable") |
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To determine the amount of address space needed by a PCI device, you must save the original value of the BAR, write a value of all 1's to the register, then read it back. The amount of memory can then be determined by masking the information bits, performing a bitwise NOT ('~' in C), and incrementing the value by 1. The original value of the BAR should then be restored. The BAR register is naturally aligned and as such you can only modify the bits that are set. For example, if a device utilizes 16 MB it will have BAR0 filled with 0xFF000000 (0x01000000 after decoding) and you can only modify the upper 8-bits. [http://www.pcisig.com/reflector/msg05233.html]
When a base address register is marked as Prefetchable, it means that the region does not have read side effects (reading from that memory range doesn't change any state), and it is allowed for the CPU to cache loads from that memory region and read it in bursts (typically cache line sized). Hardware is also allowed to merge repeated stores to the same address into one store of the latest value. If you are using paging and want maximum performance, you should map prefetchable MMIO regions as WT (write-through) instead of UC (uncacheable). On x86, frame buffers are the exception, they should be almost always be mapped WC (write-combining).
=== Class Codes ===
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