PCI: Difference between revisions
move the generic cmd/status registers to a common section, add RW/RO/RW1C flags
| [unchecked revision] | [unchecked revision] |
(Fix confusing wording in IRQ handling section) |
(move the generic cmd/status registers to a common section, add RW/RO/RW1C flags) |
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* ''Latency Timer:'' Specifies the latency timer in units of PCI bus clocks.
* ''Cache Line Size:'' Specifies the system cache line size in 32-bit units. A device can limit the number of cacheline sizes it can support, if a unsupported value is written to this field, the device will behave as if a value of 0 was written.
Remember that the PCI devices follow little ENDIAN ordering. The lower addresses contain the least significant portions of the field. Software to manipulate this structure must take particular care that the endian-ordering follows the PCI devices, not the CPUs.
===== Command Register =====
Here is the layout of the Command register:
{| {{wikitable}}
|-
! Bits 11-15 !! Bit 10 !! Bit 9 !! Bit 8 !! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bit 2 !! Bit 1 !! Bit 0
|-
| Reserved
| Interrupt Disable
| Fast Back-to-Back Enable
| SERR# Enable
| Reserved
| Parity Error Response
| VGA Palette Snoop
| Memory Write and Invalidate Enable
| Special Cycles
| Bus Master
| Memory Space
| I/O Space
|-
|
| RW
| RO
| RW
| RO
| RW
| RO
| RO
| RO
| RW
| RW
| RW
|}
* ''Interrupt Disable'' - If set to 1 the assertion of the devices INTx# signal is disabled; otherwise, assertion of the signal is enabled.
* ''Fast Back-Back Enable'' - If set to 1 indicates a device is allowed to generate fast back-to-back transactions; otherwise, fast back-to-back transactions are only allowed to the same agent.
* ''SERR# Enable'' - If set to 1 the SERR# driver is enabled; otherwise, the driver is disabled.
* ''Bit 7'' - As of revision 3.0 of the PCI local bus specification this bit is hardwired to 0. In earlier versions of the specification this bit was used by devices and may have been hardwired to 0, 1, or implemented as a read/write bit.
* ''Parity Error Response'' - If set to 1 the device will take its normal action when a parity error is detected; otherwise, when an error is detected, the device will set bit 15 of the Status register (Detected Parity Error Status Bit), but will not assert the PERR# (Parity Error) pin and will continue operation as normal.
* ''VGA Palette Snoop'' - If set to 1 the device does not respond to palette register writes and will snoop the data; otherwise, the device will trate palette write accesses like all other accesses.
* ''Memory Write and Invalidate Enable'' - If set to 1 the device can generate the Memory Write and Invalidate command; otherwise, the Memory Write command must be used.
* ''Special Cycles'' - If set to 1 the device can monitor Special Cycle operations; otherwise, the device will ignore them.
* ''Bus Master'' - If set to 1 the device can behave as a bus master; otherwise, the device can not generate PCI accesses.
* ''Memory Space'' - If set to 1 the device can respond to Memory Space accesses; otherwise, the device's response is disabled.
* ''I/O Space'' - If set to 1 the device can respond to I/O Space accesses; otherwise, the device's response is disabled.
If the kernel configures the BARs of the devices, the kernel also have to enable bits 0 and 1 for it to activate.
===== Status Register =====
Here is the layout of the Status register:
{| {{wikitable}}
|-
! Bit 15 !! Bit 14 !! Bit 13 !! Bit 12 !! Bit 11 !! Bits 9-10 !! Bit 8 !! Bit 7 !! Bit 6 !! Bit 5 !! Bit 4 !! Bit 3 !! Bits 0-2
|-
| Detected Parity Error
| Signaled System Error
| Received Master Abort
| Received Target Abort
| Signaled Target Abort
| DEVSEL Timing
| Master Data Parity Error
| Fast Back-to-Back Capable
| Reserved
| 66 MHz Capable
| Capabilities List
| Interrupt Status
| Reserved
|-
| RW1C
| RW1C
| RW1C
| RW1C
| RW1C
| RO
| RW1C
| RO
| RO
| RO
| RO
| RO
|
|}
* ''Detected Parity Error'' - This bit will be set to 1 whenever the device detects a parity error, even if parity error handling is disabled.
* ''Signalled System Error'' - This bit will be set to 1 whenever the device asserts SERR#.
* ''Received Master Abort'' - This bit will be set to 1, by a master device, whenever its transaction (except for Special Cycle transactions) is terminated with Master-Abort.
* ''Received Target Abort'' - This bit will be set to 1, by a master device, whenever its transaction is terminated with Target-Abort.
* ''Signalled Target Abort'' - This bit will be set to 1 whenever a target device terminates a transaction with Target-Abort.
* ''DEVSEL Timing'' - Read only bits that represent the slowest time that a device will assert DEVSEL# for any bus command except Configuration Space read and writes. Where a value of <code>0x0</code> represents fast timing, a value of <code>0x1</code> represents medium timing, and a value of <code>0x2</code> represents slow timing.
* ''Master Data Parity Error'' - This bit is only set when the following conditions are met. The bus agent asserted PERR# on a read or observed an assertion of PERR# on a write, the agent setting the bit acted as the bus master for the operation in which the error occurred, and bit 6 of the Command register (Parity Error Response bit) is set to 1.
* ''Fast Back-to-Back Capable'' - If set to 1 the device can accept fast back-to-back transactions that are not from the same agent; otherwise, transactions can only be accepted from the same agent.
* ''Bit 6'' - As of revision 3.0 of the PCI Local Bus specification this bit is reserved. In revision 2.1 of the specification this bit was used to indicate whether or not a device supported User Definable Features.
* ''66 MHz Capable'' - If set to 1 the device is capable of running at 66 MHz; otherwise, the device runs at 33 MHz.
* ''Capabilities List'' - If set to 1 the device implements the pointer for a New Capabilities Linked list at offset <code>0x34</code>; otherwise, the linked list is not available.
* ''Interrupt Status'' - Represents the state of the device's INTx# signal. If set to 1 and bit 10 of the Command register (Interrupt Disable bit) is set to 0 the signal will be asserted; otherwise, the signal will be ignored.
==== Header Type 0x0 ====
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| colspan="4" | 16-bit PC Card legacy mode base address
|}
=== Base Address Registers ===
| |||