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Native Intel graphics: Difference between revisions
→Programming the DPLL
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The resulting pixel clock is the quotient between the DPLL clock and a pixel multiplier. The pixel multiplier inserts padding into the SDVO output to ensure that its DPLL always operates at a frequency between 100 MHz and 200 MHz.
In order to
* Take the desired pixel clock as input.
* Chose a pixel multiplier so that the pixel clock times this multiplier is in the 100 MHz to 200 MHz range. This value is the required DPLL clock.
* Compute N, M1, M2, P1 and P2 from the DPLL clock. This can be done by iterating over all possible N, M1, M2, P1 and P2 values and checking if each combination falls into the allowed limits.
After that the DPLL can be programmed. This is done by programming the N, M1 and M2 values in <code>FPA0</code> register and programming the P1 and P2 values and enabling the DPLL in the <code>DPLLA_CTRL</code> register. Ensure to set the VGA disable bit and selecting SDVO mode.
====Programming the display pipes====
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