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The [https://nvmexpress.org/resources/specifications/ NVMe Specifications] can be found here.▼
Forum thread about this page [https://forum.osdev.org/viewtopic.php?f=8&t=36366 here].▼
== Overview ==
* NVMe controllers can be found as [[PCI]] devices with class code 1 and subclass code 8.
* Its registers are accessible through BAR 0 (it should be 64-bit memory IO).
* The controller processes commands submitted to it from "submission queues". The driver prepares commands in the queue's circular buffer in memory, and then updates the tail pointer register for the queue.
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=== PRP ===
A PRP (physical region page) is a 64-bit physical memory address. It must be DWORD aligned. A list of PRPs is used in a data transfer to specific, where data is transferred from/to in memory. A PRP list is subject to the follow rules:
* The size of the region specified by a given PRP is the minimum of: the amount of data that can be transferred without crossing a page boundary; and the amount of data remaining to be transferred.
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=== Admin commands ===
==== Create IO
* Opcode is
* The base address of the queue should be put in the DWORDs 6 and 7 of the commands.
* Command DWORD 10 contains the queue identifier in the low word, and the queue size in the high word. The queue size should be given as one less than the actual value.
* Command DWORD 11 contains flags in the low word, and the
==== Create IO
* Opcode is
* The base address of the queue should be put in the DWORDs 6 and 7 of the commands.
* Command DWORD 10 contains the queue identifier in the low word, and the queue size in the high word. The queue size should be given as one less than the actual value.
* Command DWORD 11 contains flags in the low word, and the
==== Identify ====
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* Use the submission queue ID and command ID to work out which submitted command corresponds to this completion entry.
* Update the completion queue head doorbell register.
== See Also ==
=== External Links ===
=== Forum Threads ===
[[Category:Storage]]
[[Category:Standards]]
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