Model Specific Registers: Difference between revisions
Partial undo revision 18225 by Roman (talk) - removes information not covered elsewhere
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AMD added the [[CPU_Registers_x86-64#EFER|EFER]] register for controlling specific long mode features.
{|
|Bit 0
|System Call Extensions (SCE)
|-
|Bits 1-7
|Reserved
|-
|Bit 8
|Long Mode Enable (LME)
|-
|Bit 9
|Reserved
|-
|Bit 10
|Long Mode Active (LMA)
|-
|Bit 11
|No-Execute Enable (NXE)
|-
|Bit 12
|Secure Virtual Machine Enable (SVME)
|-
|Bit 13
|Long Mode Segment Limit Enable (LMSLE)
|-
|Bit 14
|fast FXSAVE/FXSTOR (FFXSR)
|-
|Bit 15
|Translation Cache Extension (TCE)
|-
|Bits 16-63
|Reserved
|}
The by far most interesting is the SCE Bit, as it enables the <code>syscall</code> instruction.
==See Also==
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