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Processors from the P6 family onwards (including Pentium PROPentiumPro, Pentium 3II, &III, 4 and Intel Core) have a collection of registers that allowsallow configuration of variousOS-relevant things such as memory type-range, sysenter/sysexit, local APIC, etc.▼
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These '''MSRs''' are accessed using special instructions such as RDMSR (Read MSR), WRMSR (Write MSR), and RDTSC.
 
== Accessing Model Specific Registers ==
▲Processors from P6 family (including Pentium PRO, Pentium 3 & 4) have a collection of registers that allows configuration of various things such as memory type-range, sysenter/sysexit, local APIC, etc.
 
Each MSR has a single 32-bit identification number that willis beaccessed givenby tothe RDMSR orand WRMSR assemblygroup of instructions tois operateidentified itby a 32-bit integer. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by [[CPUID]].01h:EDX[bit 5 of CPUID features].
 
<syntaxhighlight lang="c">
<pre>
 
boolean cpuHasMSR()▼
const uint32_t CPUID_FLAG_MSR = 1 << 5;
 
▲booleanbool cpuHasMSR()
{
dwordstatic uint32_t a, d; // eax, edx
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
}
 
void cpuGetMSR(dworduint32_t msr, dworduint32_t *lo, dworduint32_t *hi)
{
asm volatile("rdsmrrdmsr" : "=a"(*lo), "=d"(*hi), : "c"(msr));
}
 
void cpuSetMSR(dworduint32_t msr, dworduint32_t lo, dworduint32_t hi)
{
asm volatile("wrsmrwrmsr" : : "=a"(lo), "=d"(hi), "c"(msr));
}
</syntaxhighlight>
</pre>
 
===Other way to access MSRs===
 
<code>rdmsr</code> and <code>wrmsr</code> are privileged instructions. However, there are a few MSRs that can be accessed from non-privileged code using special instructions. For example, the <code>rdtsc</code> instruction is a non-privileged instruction that reads the timestamp counter, which is actually situated in an MSR (index 10h).
 
==Additional x86_64 Registers==
 
AMD added the [[CPU_Registers_x86-64#IA32_EFER|EFER]] register for controlling specific long mode features. It has since been adopted by Intel.
 
{|
|Bit 0
|System Call Extensions (SCE)
|-
|Bits 1-7
|Reserved
|-
|Bit 8
|Long Mode Enable (LME)
|-
|Bit 9
|Reserved
|-
|Bit 10
|Long Mode Active (LMA)
|-
|Bit 11
|No-Execute Enable (NXE)
|-
|Bit 12
|Secure Virtual Machine Enable (SVME)
|-
|Bit 13
|Long Mode Segment Limit Enable (LMSLE)
|-
|Bit 14
|fast FXSAVE/FXSTOR (FFXSR)
|-
|Bit 15
|Translation Cache Extension (TCE)
|-
|Bits 16-63
|Reserved
|}
 
The by far most interesting is the SCE Bit, as it enables the <code>syscall</code> instruction.
 
==See Also==
===Articles===
*[[CPUID]]
*[[CPU Registers x86]]
*[[CPU Registers x86-64]]
 
===External Links===
*http://sandpile.org/x86/msr.htm for documented MSRs
*https://github.com/xen-project/xen/blob/master/xen/include/asm-x86/msr-index.h for MSRs relevant to Xen emulation (including Intel's 0x35)
 
[[Category:x86 CPU]]
[[Category:CPU Registers]]
[[de:Model-Specific_Register]]
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