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Model Specific Registers: Difference between revisions
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Each MSR that is accessed by the RDMSR and WRMSR group of instructions is identified by a 32-bit integer. MSRs are 64-bit wide. The presence of MSRs on your processor is indicated by [[CPUID]].01h:EDX[bit 5].
<
const uint32_t CPUID_FLAG_MSR = 1 << 5;
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bool cpuHasMSR()
{
static uint32_t a, d; // eax, edx
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
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asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
}
</syntaxhighlight>
===Other way to access MSRs===
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==Additional x86_64 Registers==
AMD added the [[CPU_Registers_x86-64#
{|
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===External Links===
*http://sandpile.org/x86/msr.htm for documented MSRs
*https://github.com/xen-project/xen/blob/master/xen/include/asm-x86/msr-index.h for MSRs relevant to Xen emulation (including Intel's 0x35)
[[Category:x86 CPU]]
[[Category:CPU Registers]]
[[de:Model-Specific_Register]]
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