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Processors from the P6 family onwards (including
These '''MSRs''' are accessed using special instructions such as RDMSR (Read MSR), WRMSR (Write MSR), and RDTSC.
== Accessing Model Specific Registers ==
Each MSR
const uint32_t CPUID_FLAG_MSR = 1 << 5;
▲<source lang="c">
bool cpuHasMSR()
{
static uint32_t a, d; // eax, edx
cpuid(1, &a, &d);
return d & CPUID_FLAG_MSR;
Line 15 ⟶ 19:
void cpuGetMSR(uint32_t msr, uint32_t *lo, uint32_t *hi)
{
asm volatile("rdmsr" : "=a"(*lo), "=d"(*hi) : "c"(msr));
}
void cpuSetMSR(uint32_t msr, uint32_t lo, uint32_t hi)
{
asm volatile("wrmsr" : : "a"(lo), "d"(hi), "c"(msr));
}
</syntaxhighlight>
==Additional x86_64 Registers==
AMD added the [[CPU_Registers_x86-64#IA32_EFER|EFER]] register for controlling specific long mode features. It has since been adopted by Intel.
{|
▲===Other access to MSRs===
|Bit 0
|System Call Extensions (SCE)
|-
|Bits 1-7
|Reserved
|-
|Bit 8
|Long Mode Enable (LME)
|-
|Bit 9
|Reserved
|-
|Bit 10
|Long Mode Active (LMA)
|-
|Bit 11
|No-Execute Enable (NXE)
|-
|Bit 12
|Secure Virtual Machine Enable (SVME)
|-
|Bit 13
|Long Mode Segment Limit Enable (LMSLE)
|-
|Bit 14
|fast FXSAVE/FXSTOR (FFXSR)
|-
|Bit 15
|Translation Cache Extension (TCE)
|-
|Bits 16-63
|Reserved
|}
The by far most interesting is the SCE Bit, as it enables the <code>syscall</code> instruction.
▲As <code>rdmsr</code> and <code>wrmsr</code> are priveleged instructions, there are a few MSRs which are deemed safe for non-priveleged access. For example, the <code>rdtsc</code> instruction is a non priveleged instruction which will read the timestamp counter which is actually situated in an MSR (index 10h).
==See Also==
===Articles===
*[[CPUID]]
*[[CPU Registers x86]]
*[[CPU Registers x86-64]]
===External Links===
*http://sandpile.org/
*https://github.com/xen-project/xen/blob/master/xen/include/asm-x86/msr-index.h for MSRs relevant to Xen emulation (including Intel's 0x35)
[[Category:x86 CPU]]
[[Category:CPU Registers]]
[[de:Model-Specific_Register]]
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