Memory Management Unit: Difference between revisions

To clarify: A processor with a MMU that provides virtual memory has an on-chip cache of "translations". Each "translation record/entry" tells the CPU the mapping of one virtual address to one physical address. Let us imaging this on-chip cache as a big lookup array of entries that are of this form:

 

// Abstract model of a TLB.

 

// Instance of a hardware Translation Lookaside Buffer.

struct tlb_cache_record_t hw_tlb[CPU_MODEL_MAX_TLB_ENTRIES];

 

Your processor's TLB is essentially a hash lookup table of entries that tell what physical address each page refers to. When you enable paging, every address reference is sent out to the TLB for lookup. The CPU does something like this internally:

A processor architecture would normally, then provide an instruction to invalidate TLB entries, either en masse, or one by one, or however the CPU designers decided. Let's try to model a TLB flush. In our model CPU architecture, there is an instruction that software can issue which will invalidate one virtual address. It is called: TLBFLSH. An OS would invoke this on our model architecture by doing something like this:

 

asm volatile ("TLBFLSH %0\n\t"::"r" (virtual_address));

 

And on to our model: