Makefile: Difference between revisions

2,970 bytes added ,  26 days ago
m
Bot: Replace deprecated source tag with syntaxhighlight
[unchecked revision][unchecked revision]
(Sometimes, "later" ''does'' come. I said "will continue tonight" and finished over 7 months later, but here it is. ;-))
m (Bot: Replace deprecated source tag with syntaxhighlight)
 
(26 intermediate revisions by 11 users not shown)
Line 1:
{{Rating|1}}
 
A Makefile is a file which controls the 'make' command. Make is available on virtually every platform, and is used to control the build process of a project. Once a Makefile has been written for a project, make can easily and efficiently build your project and create the required output file(s).
= What is a Makefile? =
 
Make reads dependency information from your Makefile, figures out which output files need (re-)building (because they are either missing or older than their corresponding input files), executes the necessary commands to actually ''do'' the (re-)building. This compares favourably to "build batchfiles" that always rebuild the whole project.
A Makefile is a file which controls the 'make' command. Make is available on virtually any platform capable of C development, and is used to control the build process of a project. Once a Makefile has been written for a project, make can easily and efficiently build your project and create the required output file(s).
 
In doing this, make is not limited to any specific set of languages. Any tool that takes some input file and generates an output file can be controlled via make.
Make reads dependency information from your Makefile, and ensure that files are built in the correct order. When source files or their dependencies have been updated, make can rebuild any affected output files - and only those, as compared to "build batches" that always rebuild the whole project.
 
While the building of a project is done with nothing more than typing 'make', aA Makefile offerscan manyoffer otherseveral features (calleddifferent "targets"), which can be invoked by 'make <target>'. A frequently-used target is 'make clean', which removes any temporary files, or 'make distinstall', which preparesinstalls athe project forin releaseits target location - but you can also give a specific output file as a target, and have make process only that file. Invoking make without a target parameter builds the default target (which is usually to build the whole project).
 
But 'make' requires a well-written Makefile to do these things efficiently and reliably.
 
= Makefile tutorial =
 
The 'make' manual will tell you about the hundreds of things you can do with a Makefile, but it doesn't give you an example for a ''good'' Makefile. The following examples are mostly shaped after the real-life [http://pdclib.e43.eu PDCLib] Makefile I used at the time, and shows some of the "tricks" used therein that may not be that obvious to the make beginner.
 
The Makefile creates only one project-wide linker library, but it should be easy to expand it for multiple binaries/libraries.
 
(Note: There are several different flavours of make around, and POSIX defines a common denominator for them. This tutorial specifically targets GNU make. See the [[Talk:Makefile#Which_make_to_target.3F | discussion page]] for further info.)
 
== Basics ==
 
It is best practice to name your makefileMakefile <code>Makefile</code> (without an extension), because when make is executed without any parameters, it will by default look for that file in the current directory. It also makes the file show up prominently on top of directory listings, at least on Unix machines.
 
Generally speaking, a makefileMakefile consists of ''definitions'' and ''rules''.
 
A ''definition'' declares a variable, and assigns a value to it. Its overallgeneral syntax is <code>VARIABLE := Value</code>.
 
'''Note:''' Frequently, you will see declarationsdefinitions withusing "=" instead of ":=". That is usually in error; suchSuch a variable declarationdefinition will result in the assignment being evaluated ''every time the variable is used''., Unlesswhile you":=" knowevaluates exactlyonly once at the startup of make, which is usually what you arewant. Don't go changing other people's doingMakefiles, usethough - ":=" foris variablea GNU extension to the make declarationssyntax.
 
A rule defines a ''target'', 0..n ''dependencies'', and 0..n ''commands''. The general idea is that ''make'' checks if the target (file) is there; if it isn't, or any of the dependencies is newer than the target, the commands are executed. The general syntax is:
 
<syntaxhighlight lang="make">
<pre>
target: dependency
command
</syntaxhighlight>
</pre>
 
Both ''dependency'' and ''command'' are optional. There might be more than one ''command'' line, in which case they are executed in sequence.
 
Note that commands ''must be tab-indented''. If your editor environment is set to replace tabs with spaces, you have to undo that setting while editing a makefileMakefile.
 
What makes makefiles so hard to read, for the beginner, is that it is not procedural in syntax (i.e., executed top-down), but functional: 'make' reads the ''whole'' makefile, building a dependency tree, and then resolves the dependencies by hopping from rule to rule as necessary until the target you gave it on the command line has successfully been resolved.
 
But let's not go into internal details of 'make'. This is a tutorial, not a man page, so it will show you how a makefile is built, and the ideas behind each line.
 
What makes Makefiles so hard to read, for the beginner, is that it is not procedural in syntax (i.e., executed top-down), but functional: 'make' reads the ''whole'' Makefile, building a dependency tree, and then resolves the dependencies by hopping from rule to rule as necessary until the target you gave it on the command line has successfully been resolved.
= Makefile Tutorial =
 
But let's not go into internal details of 'make'. This is a tutorial, not a man page, so it will show you how a real-life Makefile could be built, and the ideas behind each line.
Setting up a simple Makefile is easy. You can even go a long way ''without'' a Makefile, simply by using make's internal rulesets. Setting up a global project Makefile that works as intended is quite a bit harder.
 
The 'make' manual will tell you about the hundreds of things you can do with a Makefile, but it doesn't give you an example for a ''good'' Makefile. The following examples mainly use the [http://pdclib.rootdirectory.de/trac.fcgi/browser/trunk/Makefile PDCLib] Makefile as a template, and show some of the "tricks" used therein that may not be that obvious to the make beginner. It aims at the GNU variant of make, and uses some expressions specific to that particular make implementation (for example the patsubst function). Adaption to any special needs you might have should not be too hard once you got the idea, however.
 
The Makefile creates only one project-wide linker library, but it should be easy to expand it for multiple binaries/libraries.
 
== Automated Testing ==
Line 49:
 
As stated above, this tutorial is mainly derived from work done on the PDCLib project - which builds a single linker library. In that project, there is strictly one library function per source file. In each such source file, there is a test driver attached for conditional compilation, like this:
<syntaxhighlight lang="C">
<pre>
#ifdef TEST
int main()
Line 57:
}
#endif
</syntaxhighlight>
</pre>
Thus, when that source is compiled with ''<code>gcc -c''</code>, it results in an object file with the library function code; when compiled with ''<code>gcc -DTEST''</code>, it gives a test driver executable for that function. Returning the number of errors allows to do a grand total of errors encountered (see below).
 
== File Lists ==
Line 66:
=== Non-Source Files ===
 
<syntaxhighlight lang="make">
<pre>
# This is a list of all non-source files that are part of the distribution.
AUXFILES := Makefile Readme.txt
</syntaxhighlight>
</pre>
 
Further down we will have a target ''"dist"'', which packages all required files into a tarball for distribution. Lists of the sources and headers are created anyway. But there are commonly some auxiliary files, which are not referenced anywhere else in the Makefile but should still end up in the tarball. These are listed here.
 
=== Project Directories ===
<syntaxhighlight lang="make">
<pre>
PROJDIRS := functions includes internals
</syntaxhighlight>
</pre>
Those are subdirectories holding the actual sources. (Or rather, searched for source files automatically, see below.) These could be subprojects, or whatever. We could simply recursesearch infor anysource subdirectoryfiles starting with the current working directory, but if you like to have temporary subdirectories in your project (for testing, keeping reference sources etc.), that wouldn't work.
 
''Note that this is not a recursive approach; there is no Makefile in those subdirectories. Dependencies are hard enough to get right if you use one Makefile. At the bottom of this article is a link to a very good paper on the subject titled "recursive make considered harmful"; not only is a single Makefile easier to maintain (once you learned a couple of tricks), it's can also be more efficient!''
 
=== RecursionSources and Headers ===
<syntaxhighlight lang="make">
<pre>
SRCFILES := $(shell find $(PROJDIRS) -type f -name "\*.c")
HDRFILES := $(shell find $(PROJDIRS) -type f -name "\*.h")
</syntaxhighlight>
</pre>
It should be obvious to see what these two lines do. We now have a list of all source and header files in our project directories.
 
=== Object Files and Test Driver Executables ===
<syntaxhighlight lang="make">
<pre>
OBJFILES := $(patsubst %.c,%.o,$(SRCFILES))
TSTFILES := $(patsubst %.c,%_t,$(SRCFILES))
</syntaxhighlight>
</pre>
''OBJFILES'' should be clear - a list of the source files, with ''*.c'' exchanged for ''*.o''. ''TSTFILES'' does the same for the filename suffix ''*_t'', which we will use for our test driver executables.
 
Line 98:
 
=== Dependencies, pt. 1 ===
Many people edit their Makefile every time they add/change an ''#include'' somewhere in their code. But(Or ''GCC''forget canto do this automatically for you! Although the approach looks a little backward. For each source fileso, ''GCC'' will create a ''dependency file'' (which is canonically made to endresulting in ''*.d''), which contains a Makefile dependency rule listing that source file's includes. (And more,some butscratching seeof belowheads.)
 
But most compilers - including [[GCC]] - can do this automatically for you! Although the approach looks a little backward. For each source file, ''GCC'' will create a ''dependency file'' (which is canonically made to end in ''*.d''), which contains a Makefile dependency rule listing that source file's includes. (And more, but see below.)
 
We need two seperate sets of dependency files; one for the library objects, and one for the test driver executables (which usually have additional includes, and thus dependencies, not needed for the OBJFILES).
<syntaxhighlight lang="make">
<pre>
DEPFILES := $(patsubst %.c,%.d,$(SRCFILES))
TSTDEPFILES := $(patsubst %,%.d,$(TSTFILES))
</syntaxhighlight>
</pre>
 
=== Distribution Files ===
The last list is the one with all sources, headers, and auxiliary files that should end up in a distribution tarball.
<syntaxhighlight lang="make">
<pre>
ALLFILES := $(SRCFILES) $(HDRFILES) $(AUXFILES)
</syntaxhighlight>
</pre>
 
== .PHONY ==
The next one can take you by surprise. When you write a rule for ''make clean'', and there happens to be a file named ''clean'' in your working directory, you might be surprised to find that ''make'' does nothing, because the "target" of the rule ''clean'' already exists. To avoid this, declare such rules as ''phony'', i.e. disable the checking for a file of that name. These will be executed every time:
<syntaxhighlight lang="make">
<pre>
.PHONY: all clean dist check testdrivers todolist
</syntaxhighlight>
</pre>
 
== CFLAGS ==
If you thought ''-Wall'' does tell you everything, you'll be in for a rude surprise now. If you don't even use ''-Wall'', shame on you. ;)
<syntaxhighlight lang="make">
<pre>
WARNINGS := -Wall -Wextra -pedantic -Wshadow -Wpointer-arith -Wcast-align \
-Wwrite-strings -Wmissing-prototypes -Wmissing-declarations \
-Wredundant-decls -Wnested-externs -Winline -Wno-long-long \
-Wuninitialized -Wconversion -Wstrict-prototypes
CFLAGS := -g -std=c99gnu99 $(WARNINGS)
</syntaxhighlight>
</pre>
It is suggested to add new warning options to your project one at a time instead of all at once, to avoid getting swamped in warnings. ;) These flags are merely recommendations for C work. If you use C++, you need different ones. Check out the GCC manual; each major compiler update changes the list of available warning options.
 
Line 134 ⟶ 136:
 
=== Top-Level Targets ===
<syntaxhighlight lang="make">
<pre>
all: pdclib.a
 
pdclib.a: $(OBJFILES)
@ar r pdclib.a $?
 
clean:
-@$(RM) $(wildcard $(OBJFILES) $(DEPFILES) $(TSTFILES) pdclib.a pdclib.tgz)
 
dist:
@tar czf pdclib.tgz $(ALLFILES)
</syntaxhighlight>
</pre>
The ''@'' at the beginning of a line tells ''make'' to be quiet, i.e. not to echo the executed commands on the console prior to executing them. The Unix credo is "no news is good news". You don't get a list of processed files with ''cp'' or ''tar'', either, so it's completely beyond me why developers chose to have their Makefiles churn out endless lists of useless garbage. One very practical advantage of shutting up ''make'' is that you actually get to ''see'' those compiler warnings, instead of having them drowned out by noise.
 
Line 155 ⟶ 157:
 
=== Automated Testing, pt. 2 ===
<syntaxhighlight lang="make">
<pre>
check: testdrivers
-@rc=0; count=0; \
for file in $(TSTFILES); do \
echo " TST $$file"; ./$$file; \
rc=`expr $$rc + $$?`; count=`expr $$count + 1`; \
done; \
echo; echo "Tests executed: $$count Tests failed: $$rc"
 
testdrivers: $(TSTFILES)
</syntaxhighlight>
</pre>
Call it crude, but it works beautifully for me. The leading ''-'' means that 'make' will not abort when encountering an error, but continue with the loop.
 
Line 171 ⟶ 173:
 
=== Dependencies, pt. 2 ===
<syntaxhighlight lang="make">
<pre>
-include $(DEPFILES) $(TSTDEPFILES)
</syntaxhighlight>
</pre>
Further below, you will see how dependency files are ''generated''. Here, we ''include'' all of them, i.e. make the dependencies listed in them part of our Makefile. Never mind that they might not even exist when we run our Makefile the first time - the leading "-" again suppresses the errors.
 
=== Extracting TODO Statements ===
<syntaxhighlight lang="make">
<pre>
todolist:
-@for file in $(ALLFILES:Makefile=); do fgrep -H -e TODO -e FIXME $$file; done; true
</syntaxhighlight>
</pre>
ThisTaking all files in your project, with exception of the Makefile itself, this will ''grep'' all those ''TODO'' and ''FIXME'' comments from your files, and display them in the terminal. It is nice to be remembered of what is still missing before you do a release. To add another keyword, just insert another <code>-e keyword</code>.
 
:'''Note:''' ''$(ALLFILES:Makefile=) is a list of everything in $(ALLFILES), except for the string "Makefile" which is replaced with nothing (i.e., removed from the list). This avoids a self-referring match, where the string "TODO" in the grep command would find itself. (Of course, it also avoids finding any *real* TODO's in the Makefile, but there's always a downside. ;-) )''
 
=== Dependencies, pt. 3 ===
 
Now comes the dependency magic I talked about earlier. Note that this needs GCC 3.3 or newer.
<syntaxhighlight lang="make">
<pre>
%.o: %.c Makefile
@$(CC) $(CFLAGS) -MMD -MP -c $< -o $@
</syntaxhighlight>
</pre>
Isn't it a beauty? ;-)
 
Line 200 ⟶ 204:
Of course we also need a rule for generating the test driver executables (and their dependency files):
 
<syntaxhighlight lang="make">
<pre>
%_t: %.c Makefile pdclib.a
@$(CC) $(CFLAGS) -MMD -MP -DTEST $< pdclib.a -o $@
</syntaxhighlight>
</pre>
 
Here you can see why test driver executables get a ''*_t'' suffix instead of a ''*.t'' extension: The ''-MMD'' option uses the basename (i.e., filename without extension) of the ''compiled'' file as basis for the dependency file. If we would compile the sources into ''abc.o'' and ''abc.t'', the dependency files would both be named ''abc.d'', overwriting each other.
 
Other compilers differ a bit in their support for this, so look up their specifics when using something else than ''GCC''.
 
=== Backups ===
 
Backing up your files is a perfect candidate of a task that should be automated. However, this is generally achieved through a [[Code_Management#Version_Control_Systems|version control system]].
 
Below is an example of a ''backup'' target, which creates a dated 7-Zip archive of the directory where the Makefile resides.
 
<syntaxhighlight lang="make">
THISDIR := $(shell basename `pwd`)
TODAY := $(shell date +%Y-%m-%d)
BACKUPDIR := projectBackups/$(TODAY)
 
backup: clean
@tar cf - ../$(THISDIR) | 7za a -si ../$(BACKUPDIR)/$(THISDIR).$(TODAY)_`date +%H%M`.tar.7z
</syntaxhighlight>
 
== Summary ==
Line 221 ⟶ 242:
Luckily, 'make' allows for conditional evaluation and manual error reporting, quite akin to the C preprocessor:
 
<syntaxhighlight lang="make">
<pre>
ifndef FRAMEWORK_PATH
$(error FRAMEWORK_PATH is not set. Please set to the path where you installed "Framework".)
endif
 
ifneq ($(FRAMEWORK_PATH),/usr/lib/framework)
$(warning FRAMEWORK_PATH is set to $(FRAMEWORK_PATH), not /usr/lib/framework. Are you sure this is correct?)
endif
</syntaxhighlight>
</pre>
 
== See AlsoMulti-Target ==
 
Preliminary work has been done to write an improved Makefile, which allows generating multiple binaries with individual settings while still being easy to configure and use. While this is not yet in "tutorial" format, commented source can be found [[User:Solar/Makefile | here]].
 
=See Also=
===Articles===
* [[User:Solar/Makefile]], A more complex example capable of building multiple executables and libraries from a single Makefile.
===External Links===
* [http://jaws.rootdirectory.de JAWS], a pre-configured [http://www.cmake.org CMake] setup which, while not geared toward OS development, is a definite step forward from "naked" Makefiles.
* [http://aegis.sourceforge.net/auug97.pdf Recursive Make Considered Harmful] by Peter Miller<br />A paper detailing why the traditional approach of recursive make invocations harms performance and reliability.
* [http://www.xs4all.nl/~evbergen/nonrecursive-make.html Implementing non-recursive make] by Emile van Bergen<br />Further input on the subject of non-recursive, low-maintenance Makefile creation.
* [http://www.gnu.org/software/make/manual/ Manual for GNU make]
* [https://www.goodreads.com/book/show/583690.Managing_Projects_with_GNU_Make Managing Projects with GNU Make], the O'Reilly book on GNU Make
 
----
[[Category:Tutorials|Makefile]]
[[Category:Build Tools]]
 
[[de:Makefile]]