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MTRR: Difference between revisions
→IA32_MTRRphysBasen and IA32_MTRRphysMaskn registers
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The mask is calculated like this: <code>~(size - 1) & ((1 << ADDRESS_WIDTH) - 1)</code> where <code>ADDRESS WIDTH</code> is the maximum supported address width of your CPU. Both the mask and base must be
aligned to at least 4K boundary (thus must be shifted to the right by 12 to fit into the 51:12 range) and the size '''must''' be equal to
the boundary, on which the range is aligned. So, in order to have, for
example, a 6M-long range, one would need to set up two MTRRs, one
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