Interrupt Descriptor Table: Difference between revisions

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The '''Interrupt Descriptor Table''' ('''IDT''') is a binary data structure specific to the [[IA32_Architecture_Family|IA-32]] and [[X86-64|x86-64]] architectures. It is the '''[[Protected Mode]]''' and '''[[Long Mode]]''' counterpart to the '''[[Real Mode]]''' '''[[Interrupt Vector Table]]''' ([[IVT]]), telling the CPU where the [[Interrupt Service Routines]] (ISRsISR) are located (one per interrupt vector). It is similar to the '''[[Global Descriptor Table]]''' in structure.
 
The '''IDT''' entries are called gates. It can contain Interrupt Gates, Task Gates and Trap Gates.
 
Before you implement the '''IDT''', make sure you have a working '''GDT'''.
 
== IDTR ==
 
The location of the '''IDT''' is kept in the '''IDTR''' ('''IDT''' register). This is loaded using the '''LIDT''' assembly instruction, whose argument is a pointer to an '''IDTRIDT Descriptor''' structure:
 
{| class="wikitable"
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For more information, see '''Section 2.4.3: IDTR Interrupt Descriptor Table Register''' and '''Figure 2-6: Memory Management Registers''' of the Intel Software Developer Manual, Volume 3-A.
 
== ProtectedStructure Modeon IA-32 ==
 
=== Table ===
 
InOn '''[[Protected32-bit Mode]]'''processors, the entries in the '''IDT''' are 8 bytes long and form a table like this:
 
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* '''P:''' Present bit. Must be set ('''1''') for the descriptor to be valid.
 
For more information, see '''Section 6.11: IDT Descriptors''' and '''Figure 6-2: IDT Gate Descriptors''' of the [https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html Intel Software Developer Manual, Volume 3-A].
 
=== Example Code ===
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C Struct:
 
<sourcesyntaxhighlight lang="c">
struct InterruptDescriptor32 {
uint16_t offset_1; // offset bits 0..15
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uint16_t offset_2; // offset bits 16..31
};
</syntaxhighlight>
</source>
 
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
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* '''Task Gate: 0x85''' (p=1, dpl=0b00, type=0b0101 => type_attributes=0b1000_0101='''0x85''')
 
== LongStructure Modeon x86-64 ==
 
=== Table ===
 
InOn '''[[Long64-bit Mode]]''' (and its associated compatibility modes)processors, the entries in the '''IDT''' are 16 bytes long and form a table like this:
 
{|class="wikitable"
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C Struct:
 
<sourcesyntaxhighlight lang="c">
struct InterruptDescriptor64 {
uint16_t offset_1; // offset bits 0..15
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uint32_t zero; // reserved
};
</syntaxhighlight>
</source>
 
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
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=== Interrupt Gate ===
 
An '''Interrupt Gate''' is used to specify an '''[[Interrupt Service Routines|Interrupt Service Routine]]'''. For example, when the assembly instruction '''INT 50''' is performed while running in protected mode, the CPU looks up the 50th entry (located at 50 * 8) in the '''IDT'''. Then the Interrupt Gate's '''Selector''' and '''Offset''' values are loaded. The '''Selector''' and '''Offset''' are used to call the '''Interrupt Service Routine'''. When the '''IRET''' instruction is performed, the CPU returns from the interrupt. If the CPU was running in 32-bit mode and the specified selector is a 16-bit gate, then the CPU will go in 16-bit '''Protected Mode''' after calling the '''ISR'''. To return in this case, the '''O32 IRET''' instruction should be used, or else the CPU will not know that it should do a 32-bit return (reading 32-bit values off the [[stack]] instead of 16 bit).
 
=== Trap Gate ===