Interrupt Descriptor Table: Difference between revisions

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== IDTR ==
 
The location of the '''IDT''' is kept in the '''IDTR''' ('''IDT''' register). This is loaded using the '''LIDT''' assembly instruction, whose argument is a pointer to an '''IDTRIDT Descriptor''' structure:
 
{| class="wikitable"
Line 58:
Each entry in the table has a complex structure:
 
{| class="wikitable" style="border-width: 3px;"
|+Gate Descriptor (32-bit):
|+style="text-align: left;"|'''GATE DESCRIPTOR:'''
!style="width: 50%; text-align: left;"|63&nbsp;&nbsp;&nbsp;<span style="float: right;">48</span>
!style="width: 3.125%"|47
!style="width: 6.25%; text-align: left;"|46&nbsp;&nbsp;&nbsp;<span style="float: right;">45</span>
!style="width: 3.125%"|44
!style="width: 12.5%; text-align: left;"|43&nbsp;&nbsp;&nbsp;<span style="float: right;">40</span>
!style="width: 25%; text-align: left;"|39&nbsp;&nbsp;&nbsp;<span style="float: right;">32</span>
|-
|'''Offset'''<br>31&nbsp;&nbsp;&nbsp;<span style="float: right;">16</span>
|style="padding: 2px; width: 371px; text-align: left ; border-left: 1px ; border-right: none;"|63
|style="padding: 2px; width: 20px; text-align: rightcenter; bordervertical-leftalign: none; border-right: 1px top;"|48'''P'''
|'''DPL'''<br>1&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: center; border-left: 1px ; border-right: 1px ;"|47
|style="padding: 2px; width: 16px; text-align: left center; bordervertical-left: 1px ; border-rightalign: nonetop;"|460
|'''Gate Type'''<br>3&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 16px; text-align: right; border-left: none; border-right: 1px ;"|45
|style="vertical-align:top"|Reserved
|style="padding: 2px; width: 19px; text-align: center; border-left: 1px ; border-right: 1px ;"|44
|style="padding: 2px; width: 71px; text-align: left ; border-left: 1px ; border-right: none;"|43
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|40
|style="padding: 2px; width: 171px; text-align: left ; border-left: 1px ; border-right: none;"|39
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|32
|-
|style="padding: 2px; width: 371px; text-align: left ; border-left: 1px ; border-right: none;"|'''Offset'''<br>31
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|<br>16
|style="padding: 2px; width: 20px; text-align: center; border-left: 1px ; border-right: 1px ;"|'''P'''<br>&#8203;
|style="padding: 2px; width: 16px; text-align: left ; border-left: 1px ; border-right: none;"|'''DPL'''<br>1
|style="padding: 2px; width: 16px; text-align: right; border-left: none; border-right: 1px ;"|<br>0
|style="padding: 2px; width: 19px; text-align: center; border-left: 1px ; border-right: 1px ;"|0<br>&#8203;
|style="padding: 2px; width: 71px; text-align: left ; border-left: 1px ; border-right: none;"|'''Gate Type'''<br>3
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|<br>0
|style="padding: 2px; width: 171px; text-align: left ; border-left: 1px ; border-right: none;"|Reserved<br>&#8203;
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|
|}
{| class="wikitable" style="border-width: 3px;"
|-
!style="text-align: left;" |31&nbsp;&nbsp;&nbsp;<span style="float: right;">16</span>
|style="padding: 2px; width: 371px; border-right: none;" |31
!style="text-align: left;" colspan="5" |15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |16
|style="padding: 2px; width: 371px; border-right: none;" |15
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |0
|-
|'''Segment Selector'''<br>15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 371px; border-right: none;" |'''Segment Selector'''<br>15
|colspan="5" |'''Offset'''<br>15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |<br>0
|style="padding: 2px; width: 371px; border-right: none;" |'''Offset'''<br>15
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |<br>0
|}
 
* '''Offset:''' A 32-bit value, split in two parts. It represents the address of the entry point of the '''[[Interrupt Service Routines|Interrupt Service Routine]]'''.
* '''Selector:''' A 16-bit'''[[Segment valueSelector]]''' with multiple fields which must point to a valid code segment in your '''[[GDT]]'''. For more information, see the [[Segment selector|Segment selector]] page or '''Section 3.4.2: Segment Selectors''' and '''Figure 3-6: Segment Selector''' of the Intel Software Developer Manual, Volume 3-A.
* '''Gate Type:''' A 4-bit value which defines the type of gate this '''Interrupt Descriptor''' represents. There are five valid type values:
** '''0b0101''' or '''0x5''': Task Gate, note that in this case, the '''Offset''' value is unused and should be set to zero.
Line 107 ⟶ 92:
* '''P:''' Present bit. Must be set ('''1''') for the descriptor to be valid.
 
For more information, see '''Section 6.11: IDT Descriptors''' and '''Figure 6-2: IDT Gate Descriptors''' of the [https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html Intel Software Developer Manual, Volume 3-A].
 
=== Example Code ===
Line 113 ⟶ 98:
C Struct:
 
<sourcesyntaxhighlight lang="c">
struct InterruptDescriptor32 {
uint16_t offset_1; // offset bits 0..15
Line 121 ⟶ 106:
uint16_t offset_2; // offset bits 16..31
};
</syntaxhighlight>
</source>
 
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
Line 155 ⟶ 140:
Each entry in the table has a complex structure:
 
{| class="wikitable" style="border-width: 3px;"
|+Gate Descriptor (64-bit):
|+style="text-align: left;"|'''GATE DESCRIPTOR:'''
!colspan="7" style="text-align: left;"|127&nbsp;&nbsp;&nbsp;<span style="float: right;">96</span>
|-
|colspan="7" |Reserved
|style="padding: 2px; width: 771px; border-right: none;" |127
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |96
|-
!colspan="7" style="text-align: left;"|95&nbsp;&nbsp;&nbsp;<span style="float: right;">64</span>
|style="padding: 2px; width: 771px; border-right: none;" |Reserved<br>&#8203;
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |
|}
{| class="wikitable" style="border-width: 3px;"
|-
|colspan="7" |'''Offset'''<br>63&nbsp;&nbsp;&nbsp;<span style="float: right;">32</span>
|style="padding: 2px; width: 771px; border-right: none;" |95
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |64
|-
!style="width: 50%; text-align: left;"|63&nbsp;&nbsp;&nbsp;<span style="float: right;">48</span>
|style="padding: 2px; width: 771px; border-right: none;" |'''Offset'''<br>63
!style="width: 3.125%"|47
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |<br>32
!style="width: 6.25%; text-align: left;"|46&nbsp;&nbsp;&nbsp;<span style="float: right;">45</span>
|}
{| class="wikitable" !style="border-width: 3px;3.125%"|44
!style="width: 12.5%; text-align: left;"|43&nbsp;&nbsp;&nbsp;<span style="float: right;">40</span>
!style="width: 15.625%; text-align: left;"|39&nbsp;&nbsp;&nbsp;<span style="float: right;">35</span>
!style="width: 9.375%; text-align: left;"|34&nbsp;&nbsp;&nbsp;<span style="float: right;">32</span>
|-
|'''Offset'''<br>31&nbsp;&nbsp;&nbsp;<span style="float: right;">16</span>
|style="padding: 2px; width: 371px; text-align: left ; border-left: 1px ; border-right: none;"|63
|style="padding: 2px; width: 20px; text-align: rightcenter; bordervertical-leftalign: none; border-right: 1px top;"|48'''P'''
|'''DPL'''<br>1&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: center; border-left: 1px ; border-right: 1px ;"|47
|style="padding: 2px; width: 16px; text-align: left center; bordervertical-left: 1px ; border-rightalign: nonetop;"|460
|'''Gate Type'''<br>3&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 16px; text-align: right; border-left: none; border-right: 1px ;"|45
|style="vertical-align:top"|Reserved
|style="padding: 2px; width: 19px; text-align: center; border-left: 1px ; border-right: 1px ;"|44
|'''IST'''<br>2&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 71px; text-align: left ; border-left: 1px ; border-right: none;"|43
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|40
|style="padding: 2px; width: 171px; text-align: left ; border-left: 1px ; border-right: none;"|39
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|32
|-
|style="padding: 2px; width: 371px; text-align: left ; border-left: 1px ; border-right: none;"|'''Offset'''<br>31
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|<br>16
|style="padding: 2px; width: 20px; text-align: center; border-left: 1px ; border-right: 1px ;"|'''P'''<br>&#8203;
|style="padding: 2px; width: 16px; text-align: left ; border-left: 1px ; border-right: none;"|'''DPL'''<br>1
|style="padding: 2px; width: 16px; text-align: right; border-left: none; border-right: 1px ;"|<br>0
|style="padding: 2px; width: 19px; text-align: center; border-left: 1px ; border-right: 1px ;"|0<br>&#8203;
|style="padding: 2px; width: 71px; text-align: left ; border-left: 1px ; border-right: none;"|'''Gate Type'''<br>3
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|<br>0
|style="padding: 2px; width: 171px; text-align: left ; border-left: 1px ; border-right: none;"|Reserved<br>&#8203;
|style="padding: 2px; width: 20px; text-align: right; border-left: none; border-right: 1px ;"|
|}
{| class="wikitable" style="border-width: 3px;"
|-
!style="text-align: left;" |31&nbsp;&nbsp;&nbsp;<span style="float: right;">16</span>
|style="padding: 2px; width: 371px; border-right: none;" |31
!style="text-align: left;" colspan="6" |15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |16
|style="padding: 2px; width: 371px; border-right: none;" |15
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |0
|-
|'''Segment Selector'''<br>15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 371px; border-right: none;" |'''Segment Selector'''<br>15
|colspan="6" |'''Offset'''<br>15&nbsp;&nbsp;&nbsp;<span style="float: right;">0</span>
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |<br>0
|style="padding: 2px; width: 371px; border-right: none;" |'''Offset'''<br>15
|style="padding: 2px; width: 20px; text-align: right; border-left: none;" |<br>0
|}
 
* '''Offset:''' A 64-bit value, split in three parts. It represents the address of the entry point of the '''[[Interrupt Service Routines|Interrupt Service Routine]]'''.
* '''Selector:''' A 16-bit'''[[Segment valueSelector]]''' with multiple fields which must point to a valid 64-bit code segment in your '''[[GDT]]'''. For more information, see '''Section 3.4.2: Segment Selectors''' and '''Figure 3-6: Segment Selector''' of the Intel Software Developer Manual, Volume 3-A.
* '''IST:''' A 3-bit value which is an offset into the '''Interrupt Stack Table''', which is stored in the '''[[Task State Segment]]'''. If the bits are all set to zero, the '''Interrupt Stack Table''' is not used.
* '''Gate Type:''' A 4-bit value which defines the type of gate this '''Interrupt Descriptor''' represents. In long mode there are two valid type values:
Line 226 ⟶ 190:
C Struct:
 
<sourcesyntaxhighlight lang="c">
struct InterruptDescriptor64 {
uint16_t offset_1; // offset bits 0..15
Line 236 ⟶ 200:
uint32_t zero; // reserved
};
</syntaxhighlight>
</source>
 
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
Line 248 ⟶ 212:
=== Interrupt Gate ===
 
An '''Interrupt Gate''' is used to specify an '''[[Interrupt Service Routines|Interrupt Service Routine]]'''. For example, when the assembly instruction '''INT 50''' is performed while running in protected mode, the CPU looks up the 50th entry (located at 50 * 8) in the '''IDT'''. Then the Interrupt Gate's '''Selector''' and '''Offset''' values are loaded. The '''Selector''' and '''Offset''' are used to call the '''Interrupt Service Routine'''. When the '''IRET''' instruction is performed, the CPU returns from the interrupt. If the CPU was running in 32-bit mode and the specified selector is a 16-bit gate, then the CPU will go in 16-bit '''Protected Mode''' after calling the '''ISR'''. To return in this case, the '''O32 IRET''' instruction should be used, or else the CPU will not know that it should do a 32-bit return (reading 32-bit values off the [[stack]] instead of 16 bit).
 
=== Trap Gate ===