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The '''Interrupt Descriptor Table''' ('''IDT''') is a binary data structure specific to the [[IA32_Architecture_Family|IA-32]] and [[X86-64|x86-64]] architectures. It is the [[Protected Mode]] and Long Mode counterpart to the [[Real Mode]] Interrupt Vector Table ([[IVT]]) telling the CPU where the [[Interrupt Service Routines]] (ISR) are located (one per interrupt vector). It is similar to the [[Global Descriptor Table]] in structure.
The IDT entries are called gates. It can contain Interrupt Gates, Task Gates and Trap Gates.
Before you implement the IDT, make sure you have a working GDT.
== IDTR ==
The location of the '''IDT''' is kept in the '''IDTR''' ('''IDT''' register). This is loaded using the '''LIDT''' assembly instruction, whose argument is a pointer to an '''IDT Descriptor''' structure:
{| class="wikitable"
|+IDT Descriptor (IDTR):
!style="width: 66%; text-align: left;" |79 (64-bit Mode)<br>48 (32-bit Mode) <span style="float: right;">16</span>
!style="width: 34%; text-align: left; vertical-align: bottom;" |15 <span style="float: right;">0</span>
|-
|'''Offset'''<br>63 (64-bit Mode)<br>31 (32-bit Mode) <span style="float: right;">0</span>
|'''Size'''<br><br>15 <span style="float: right;">0</span>
|}
* '''Size''': One less than the size of the '''IDT''' in bytes.
* '''Offset''': The linear address of the '''Interrupt Descriptor Table''' (not the physical address, paging applies).
Note that the amount of data loaded by '''LIDT''' differs in 32-bit and 64-bit modes, '''Offset''' is 4 bytes long in 32-bit mode and 8 bytes long in 64-bit mode.
This is similar to the '''[[GDT]]''', except:
* The first entry (at zero offset) is used in the '''IDT'''.
* There are 256 interrupt vectors (0..255), so the '''IDT''' should have 256 entries, each entry corresponding to a specific interrupt vector.
* Although the '''IDT''' can contain more than 256 entries, they are ignored.
* Although the '''IDT''' can contain less than 256 entries, any entries that are not present (due to this or other reasons) will generate a '''[[Exceptions#General Protection Fault|General Protection Fault]]''' when an attempt to access them is made. Ideally the '''IDT''' should contain enough entries so that this fault (which is itself an interrupt vector) can be handled.
For more information, see '''Section 2.4.3: IDTR Interrupt Descriptor Table Register''' and '''Figure 2-6: Memory Management Registers''' of the Intel Software Developer Manual, Volume 3-A.
== Structure on IA-32 ==
=== Table ===
On 32-bit processors, the entries in the '''IDT''' are 8 bytes long and form a table like this:
{|class="wikitable"
|+Interrupt Descriptor Table (32-bit)
! Address !! Content
|-
| IDTR Offset + 0 || Entry 0
|-
| IDTR Offset + 8 || Entry 1
|-
| IDTR Offset + 16 || Entry 2
|- style="text-align: center;"
| '''...''' || '''...'''
|-
| IDTR Offset + 2040 || Entry 255
|}
The corresponding entry for a given '''Interrupt Vector''' is pointed to in memory by scaling the vector by 8 and adding it to the value in the '''Offset''' field of the '''IDTR'''.
=== Gate Descriptor ===
Each entry in the table has a complex structure:
{| class="wikitable"
|+Gate Descriptor (32-bit):
!style="width: 50%; text-align: left;"|63 <span style="float: right;">48</span>
!style="width: 3.125%"|47
!style="width: 6.25%; text-align: left;"|46 <span style="float: right;">45</span>
!style="width: 3.125%"|44
!style="width: 12.5%; text-align: left;"|43 <span style="float: right;">40</span>
!style="width: 25%; text-align: left;"|39 <span style="float: right;">32</span>
|-
|'''Offset'''<br>31 <span style="float: right;">16</span>
|style="text-align: center; vertical-align: top;"|'''P'''
|'''DPL'''<br>1 <span style="float: right;">0</span>
|style="text-align: center; vertical-align: top;"|0
|'''Gate Type'''<br>3 <span style="float: right;">0</span>
|style="vertical-align:top"|Reserved
|-
!style="text-align: left;" |31 <span style="float: right;">16</span>
!style="text-align: left;" colspan="5" |15 <span style="float: right;">0</span>
|-
|'''Segment Selector'''<br>15 <span style="float: right;">0</span>
|colspan="5" |'''Offset'''<br>15 <span style="float: right;">0</span>
|}
* '''Offset:''' A 32-bit value, split in two parts. It represents the address of the entry point of the '''[[Interrupt Service Routines|Interrupt Service Routine]]'''.
* '''Selector:''' A '''[[Segment Selector]]''' with multiple fields which must point to a valid code segment in your '''[[GDT]]'''.
* '''Gate Type:''' A 4-bit value which defines the type of gate this '''Interrupt Descriptor''' represents. There are five valid type values:
** '''0b0101''' or '''0x5''': Task Gate, note that in this case, the '''Offset''' value is unused and should be set to zero.
** '''0b0110''' or '''0x6''': 16-bit Interrupt Gate
** '''0b0111''' or '''0x7''': 16-bit Trap Gate
** '''0b1110''' or '''0xE''': 32-bit Interrupt Gate
** '''0b1111''' or '''0xF''': 32-bit Trap Gate
* '''DPL:''' A 2-bit value which defines the '''[[Security#Rings|CPU Privilege Levels]]''' which are allowed to access this interrupt via the '''INT''' instruction. Hardware interrupts ignore this mechanism.
* '''P:''' Present bit. Must be set ('''1''') for the descriptor to be valid.
For more information, see '''Section 6.11: IDT Descriptors''' and '''Figure 6-2: IDT Gate Descriptors''' of the [https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.html Intel Software Developer Manual, Volume 3-A].
=== Example Code ===
C Struct:
<syntaxhighlight lang="c">
struct InterruptDescriptor32 {
uint16_t offset_1; // offset bits 0..15
uint16_t selector; // a code segment selector in GDT or LDT
uint8_t zero; // unused, set to 0
uint8_t type_attributes; // gate type, dpl, and p fields
uint16_t offset_2; // offset bits 16..31
};
</syntaxhighlight>
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
* 32-bit '''Interrupt Gate: 0x8E''' (p=1, dpl=0b00, type=0b1110 => type_attributes=0b1000_1110='''0x8E''')
* 32-bit '''Trap Gate: 0x8F''' (p=1, dpl=0b00, type=0b1111 => type_attributes=1000_1111b='''0x8F''')
* '''Task Gate: 0x85''' (p=1, dpl=0b00, type=0b0101 => type_attributes=0b1000_0101='''0x85''')
== Structure on x86-64 ==
=== Table ===
On 64-bit processors, the entries in the '''IDT''' are 16 bytes long and form a table like this:
{|class="wikitable"
|+Interrupt Descriptor Table (64-bit)
! Address !! Content
|-
| IDTR Offset + 0 || Entry 0
|-
| IDTR Offset + 16 || Entry 1
|-
| IDTR Offset + 32 || Entry 2
|- style="text-align: center;"
| '''...''' || '''...'''
|-
| IDTR Offset + 4080 || Entry 255
|}
The corresponding entry for a given '''Interrupt Vector''' is pointed to in memory by scaling the vector by 16 and adding it to the value in the '''Offset''' field of the '''IDTR'''.
=== Gate Descriptor ===
Each entry in the table has a complex structure:
{| class="wikitable"
|+Gate Descriptor (64-bit):
!colspan="7" style="text-align: left;"|127 <span style="float: right;">96</span>
|-
|colspan="7" |Reserved
|-
!colspan="7" style="text-align: left;"|95 <span style="float: right;">64</span>
|-
|colspan="7" |'''Offset'''<br>63 <span style="float: right;">32</span>
|-
!style="width: 50%; text-align: left;"|63 <span style="float: right;">48</span>
!style="width: 3.125%"|47
!style="width: 6.25%; text-align: left;"|46 <span style="float: right;">45</span>
!style="width: 3.125%"|44
!style="width: 12.5%; text-align: left;"|43 <span style="float: right;">40</span>
!style="width: 15.625%; text-align: left;"|39 <span style="float: right;">35</span>
!style="width: 9.375%; text-align: left;"|34 <span style="float: right;">32</span>
|-
|'''Offset'''<br>31 <span style="float: right;">16</span>
|style="text-align: center; vertical-align: top;"|'''P'''
|'''DPL'''<br>1 <span style="float: right;">0</span>
|style="text-align: center; vertical-align: top;"|0
|'''Gate Type'''<br>3 <span style="float: right;">0</span>
|style="vertical-align:top"|Reserved
|'''IST'''<br>2 <span style="float: right;">0</span>
|-
!style="text-align: left;" |31 <span style="float: right;">16</span>
!style="text-align: left;" colspan="6" |15 <span style="float: right;">0</span>
|-
|'''Segment Selector'''<br>15 <span style="float: right;">0</span>
|colspan="6" |'''Offset'''<br>15 <span style="float: right;">0</span>
|}
* '''Offset:''' A 64-bit value, split in three parts. It represents the address of the entry point of the '''[[Interrupt Service Routines|Interrupt Service Routine]]'''.
* '''Selector:''' A '''[[Segment Selector]]''' with multiple fields which must point to a valid code segment in your '''[[GDT]]'''.
* '''IST:''' A 3-bit value which is an offset into the '''Interrupt Stack Table''', which is stored in the '''[[Task State Segment]]'''. If the bits are all set to zero, the '''Interrupt Stack Table''' is not used.
* '''Gate Type:''' A 4-bit value which defines the type of gate this '''Interrupt Descriptor''' represents. In long mode there are two valid type values:
** '''0b1110''' or '''0xE''': 64-bit Interrupt Gate
** '''0b1111''' or '''0xF''': 64-bit Trap Gate
* '''DPL:''' A 2-bit value which defines the '''[[Security#Rings|CPU Privilege Levels]]''' which are allowed to access this interrupt via the '''INT''' instruction. Hardware interrupts ignore this mechanism.
* '''P:''' Present bit. Must be set ('''1''') for the descriptor to be valid.
In your '''[[Interrupt Service Routines|Interrupt Service Routines]]''', remember to return from the interrupt using the '''IRETQ''' instruction instead of '''IRET''', as assemblers will not translate that for you. Many 64-bit IDT related problems on the forum are caused by that missing 'Q'. Don't let this happen to you.
For more information, see '''Section 6.14.1: 64-Bit Mode IDT''' and '''Figure 6-8: 64-Bit IDT Gate Descriptors''' of the Intel Software Developer Manual, Volume 3-A.
=== Example Code ===
C Struct:
<syntaxhighlight lang="c">
struct InterruptDescriptor64 {
uint16_t offset_1; // offset bits 0..15
uint16_t selector; // a code segment selector in GDT or LDT
uint8_t ist; // bits 0..2 holds Interrupt Stack Table offset, rest of bits zero.
uint8_t type_attributes; // gate type, dpl, and p fields
uint16_t offset_2; // offset bits 16..31
uint32_t offset_3; // offset bits 32..63
uint32_t zero; // reserved
};
</syntaxhighlight>
Example ''type_attributes'' values that people are likely to use (assuming DPL is 0):
* 64-bit '''Interrupt Gate: 0x8E''' (p=1, dpl=0b00, type=0b1110 => type_attributes=0b1000_1110='''0x8E''')
* 64-bit '''Trap Gate: 0x8F''' (p=1, dpl=0b00, type=0b1111 => type_attributes=1000_1111b='''0x8F''')
== Gate Types ==
There are basically two kinds of interrupts: ones that occur when code execution has encountered an '''[[Exceptions|Exception]]''' due to bad code, or ones that occur to handle events unrelated to currently executing code. In the first case it is pertinent to save the address of the ''currently'' executing instruction so that it can be retried, these are called '''Traps'''. In the second case it is pertinent to save the address of the ''next'' instruction so that execution can be resumed where it left off. These could be caused by an IRQ or other hardware event, or by use of the '''INT''' instruction. Another difference to note is that with '''Traps''', new interrupts might occur during the service routine, but when the CPU is serving an IRQ, further interrupts are masked until an '''End of Interrupt''' signal is sent. How a certain interrupt is served depends on which kind of gate you put in the IDT entry.
=== Interrupt Gate ===
An '''Interrupt Gate''' is used to specify an '''[[Interrupt Service Routines|Interrupt Service Routine]]'''. For example, when the assembly instruction '''INT 50''' is performed while running in protected mode, the CPU looks up the 50th entry (located at 50 * 8) in the '''IDT'''. Then the Interrupt Gate's '''Selector''' and '''Offset''' values are loaded. The '''Selector''' and '''Offset''' are used to call the '''Interrupt Service Routine'''. When the '''IRET''' instruction is performed, the CPU returns from the interrupt. If the CPU was running in 32-bit mode and the specified selector is a 16-bit gate, then the CPU will go in 16-bit Protected Mode after calling the '''ISR'''. To return in this case, the '''O32 IRET''' instruction should be used, or else the CPU will not know that it should do a 32-bit return (reading 32-bit values off the [[stack]] instead of 16 bit).
=== Trap Gate ===
A '''Trap Gate''' should be used to handle '''[[Exceptions|Exceptions]]'''. When such an exception occurs, there can sometimes be an error code placed on the stack, which should be popped before returning from the interrupt.
'''Trap Gates''' and '''Interrupt Gates''' are similar, and their descriptors are structurally the same, differing only in the '''Gate Type''' field. The difference is that for '''Interrupt Gates''', interrupts are automatically disabled upon entry and reenabled upon '''IRET''', whereas this does not occur for '''Trap Gates'''.
=== Task Gate ===
A '''Task Gate''' is a gate type specific to IA-32 that is used for hardware task switching. For a '''Task Gate''' the '''Selector''' value should refer to a position in the '''[[GDT]]''' which specifies a '''[[Task State Segment]]''' rather than a code segment, and the '''Offset''' value is unused and should be set to zero. Rather than jumping to a service routine, when the CPU processes this interrupt, it will perform a hardware task switch to the specified task. A pointer back to the task which was interrupted will be stored in the '''Task Link''' field in the '''TSS'''.
{{Quotation|"*NOTE* Because IA-32 tasks are not re-entrant, an interrupt-handler task must disable interrupts between the time it completes handling the interrupt and the time it executes the IRET instruction. This action prevents another interrupt from occurring while the interrupt task's TSS is still marked busy, which would cause a general-protection (#GP) exception."|Intel Software Developer Manual}}
This type of gate is not often used as hardware task switching is slow and has little to no optimization on modern processors. As well, it has been entirely removed on [[X86-64|x86-64]].
==See Also==
===Articles===
* [[GDT]]
* [[IDT_problems|IDT problems]]
=== External
* [http://www.logix.cz/michal/doc/i386/chp09-00.htm Michal Ludvig's Intel 80386 Programmer's Reference Manual chapter 9]
[[Category:X86 CPU]]
[[Category:Interrupts]]
[[de:Interrupt_Descriptor_Table]]
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