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Intel High Definition Audio: Difference between revisions
→Device Registers
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m (→Setting up the AFG codec: corrections to steps (1) and (2)) |
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! Name
! Description
! Notes
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| 00 || GCAP || Global Capabilities || (includes number of DMA engines for input and output streams)
Line 41 ⟶ 42:
| 0C || WAKEEN || Wake Enable ||
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| 0E || STATESTS || State Change Status ||
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| 10 || GSTS || Global Status ||
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| 18 || OUTSTRMPAY || Output Stream Payload Capability ||
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| 1A || INSTRMPAY || Input Stream Payload Capability ||
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| 20 || INTCTL || Interrupt Control ||
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| 24 || INTSTS || Interrupt Status ||
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| 30 || COUNTER || Wall Clock Counter ||
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| 38 || SSYNC || Stream Synchronization || (set bits 0-29 to pause DMA streams 1-30)
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| 40 || CORBLBASE || CORB Lower Base Address || (command output ring buffer address)
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| 44 || CORBUBASE || CORB Upper Base Address ||
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| 48 || CORBWP || CORB Write Pointer ||
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| 4a || CORBRP || CORB Read Pointer ||
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| 4c || CORBCTL || CORB Control ||
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| 4d || CORBSTS || CORB Status ||
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| 4e || CORBSIZE || CORB Size ||
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| 50 || RIRBLBASE || RIRB Lower Base Address || (response input ring buffer address)
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| 54 || RIRBUBASE || RIRB Upper Base Address ||
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| 58 || RIRBWP || RIRB Write Pointer ||
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| 5a || RINTCNT || Response Interrupt Count ||
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| 5c || RIRBCTL || RIRB Control ||
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| 5d || RIRBSTS || RIRB Status ||
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| 5e || RIRBSIZE || RIRB Size ||
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| 60 || || Immediate Command Output Interface ||
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| 64 || || Immediate Response Input Interface ||
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| 68 || || Immediate Command Status ||
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| 70 || DPLBASE || DMA Position Lower Base Address ||
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| 74 || DPUBASE || DMA Position Upper Base Address ||
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| 80 || || Stream Descriptors ||
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