Intel High Definition Audio: Difference between revisions

[unchecked revision][unchecked revision]
Content deleted Content added
Corrected error about amplifier gain values.
Fixed incorrect SSYNC offset.
Line 56:
| 30 || COUNTER || Wall Clock Counter ||
|-
| 3834 || SSYNC || Stream Synchronization || (set bits 0-29 to pause DMA streams 1-30)
Note: The HD Audio specifications list this register at offset 0x38, but this appears to be incorrect.
|-
| 40 || CORBLBASE || CORB Lower Base Address || (command output ring buffer address)