Intel Ethernet i217: Difference between revisions

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{{FirstPerson}}
== Network Driver for Intel Ethernet Cards I217 and 82577LM ==
 
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It is very important to highlight that this wiki does not utilize all the features in the above NICs, but it show how to configure the NICs for basic functionality such as initialization, read packets, and write packets.
 
== Card Addresses and Data Structures ==
 
To start with, lets state some macro definitions that we are going to use in the code.
<sourcesyntaxhighlight lang="c">
 
#define INTEL_VEND 0x8086 // Vendor ID for Intel
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#define REG_RDTR 0x2820 // RX Delay Timer Register
#define REG_RXDCTL 0x38280x2828 // RX Descriptor Control
#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
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#define TSTA_LC (1 << 2) // Late Collision
#define LSTA_TU (1 << 3) // Transmit Underrun
</syntaxhighlight>
</source>
 
Now lets define the data structures for the transmit and receive buffers
 
<sourcesyntaxhighlight lang="c">
 
#define E1000_NUM_RX_DESC 32
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} __attribute__((packed));
 
</syntaxhighlight>
</source>
 
And finally some helper macrosstatic methods for MMIO read/write operations and Ports I/O
 
<sourcesyntaxhighlight lang="c">
#define mmio_read32(p) (*((volatile uint32_t*)(p)))
#define mmio_write32(p,v) ((*((volatile uint32_t*)(p)))=(v))
#define mmio_read16(p) (*((volatile uint16_t*)(p)))
#define mmio_write16(p,v) ((*((volatile uint16_t*)(p)))=(v))
#define mmio_read8(p) (*((volatile uint8_t*)(p)))
#define mmio_write8(p,v) ((*((volatile uint8_t*)(p)))=(v))
</source>
 
class MMIOUtils
{
public:
static uint8_t read8 (uint64_t p_address);
static uint16_t read16 (uint64_t p_address);
static uint32_t read32 (uint64_t p_address);
static uint64_t read64 (uint64_t p_address);
static void write8 (uint64_t p_address,uint8_t p_value);
static void write16 (uint64_t p_address,uint16_t p_value);
static void write32 (uint64_t p_address,uint32_t p_value);
static void write64 (uint64_t p_address,uint64_t p_value);
};
 
 
uint8_t MMIOUtils::read8 (uint64_t p_address)
{
return *((volatile uint8_t*)(p_address));
}
uint16_t MMIOUtils::read16 (uint64_t p_address)
{
return *((volatile uint16_t*)(p_address));
}
uint32_t MMIOUtils::read32 (uint64_t p_address)
{
return *((volatile uint32_t*)(p_address));
}
uint64_t MMIOUtils::read64 (uint64_t p_address)
{
return *((volatile uint64_t*)(p_address));
}
void MMIOUtils::write8 (uint64_t p_address,uint8_t p_value)
{
(*((volatile uint8_t*)(p_address)))=(p_value);
}
void MMIOUtils::write16 (uint64_t p_address,uint16_t p_value)
{
(*((volatile uint16_t*)(p_address)))=(p_value);
}
void MMIOUtils::write32 (uint64_t p_address,uint32_t p_value)
{
(*((volatile uint32_t*)(p_address)))=(p_value);
}
void MMIOUtils::write64 (uint64_t p_address,uint64_t p_value)
{
(*((volatile uint64_t*)(p_address)))=(p_value);
}
 
</syntaxhighlight>
 
<syntaxhighlight lang="c">
#ifndef PORTS_H_
#define PORTS_H_
 
 
class Ports
{
private:
public:
static void outportb (uint16_t p_port,uint8_t data);
static void outportw (uint16_t p_port,uint16_t data);
static void outportl (uint16_t p_port,uint32_t data);
static uint8_t inportb( uint16_t p_port);
static uint16_t inportw( uint16_t p_port);
static uint32_t inportl( uint16_t p_port);
};
 
#endif /* PORTS_H_ */
 
 
/* void Ports::outportb (uint16_t p_port,uint8_t p_data)
*
* This method outputs a byte to a hardware port.
* It uses an inline asm with the volatile keyword
* to disable compiler optimization.
*
* p_port: the port number to output the byte p_data to.
* p_data: the byte to to output to the port p_port.
*
* Notice the input constraint
* "dN" (port) : indicates using the DX register to store the
* value of port in it
* "a" (data) : store the value of data into
*
* The above constraint will instruct the compiler to generate assembly
* code that looks like that
* mov %edi,%edx
* mov %esi,%eax
* out %eax,(%dx)
*
* According the ABI, the edi will have the value of p_port and esi will have
* the value of the p_data
*
*/
void Ports::outportb (uint16_t p_port,uint8_t p_data)
{
asm volatile ("outb %1, %0" : : "dN" (p_port), "a" (p_data));
}
 
/* void Ports::outportw (uint16_t p_port,uint16_t p_data)
*
* This method outputs a word to a hardware port.
*
* p_port: the port number to output the byte p_data to.
* p_data: the byte to to output to the port p_port.
*
*/
 
 
void Ports::outportw (uint16_t p_port,uint16_t p_data)
{
asm volatile ("outw %1, %0" : : "dN" (p_port), "a" (p_data));
}
 
/* void Ports::outportl (uint16_t p_port,uint32_t p_data)
*
* This method outputs a double word to a hardware port.
*
* p_port: the port number to output the byte p_data to.
* p_data: the byte to to output to the port p_port.
*
*/
 
 
void Ports::outportl (uint16_t p_port,uint32_t p_data)
{
asm volatile ("outl %1, %0" : : "dN" (p_port), "a" (p_data));
}
 
/* uint8_t Ports::inportb( uint16_t p_port)
*
* This method reads a byte from a hardware port.
*
* p_port: the port number to read the byte from.
* return value : a byte read from the port p_port.
*
* Notice the output constraint "=a", this tells the compiler
* to expect the save the value of register AX into the variable l_ret
* The register AX should contain the result of the inb instruction.
*
*
*/
 
uint8_t Ports::inportb( uint16_t p_port)
{
uint8_t l_ret;
asm volatile("inb %1, %0" : "=a" (l_ret) : "dN" (p_port));
return l_ret;
}
 
/* uint16_t Ports::inportw( uint16_t p_port)
*
* This method reads a word from a hardware port.
*
* p_port: the port number to read the word from.
* return value : a word read from the port p_port.
*
*/
 
 
uint16_t Ports::inportw( uint16_t p_port)
{
uint16_t l_ret;
asm volatile ("inw %1, %0" : "=a" (l_ret) : "dN" (p_port));
return l_ret;
}
 
 
/* uint16_t Ports::inportl( uint16_t p_port)
*
* This method reads a double word from a hardware port.
*
* p_port: the port number to read the double word from.
* return value : a double word read from the port p_port.
*
*/
 
uint32_t Ports::inportl( uint16_t p_port)
{
uint32_t l_ret;
asm volatile ("inl %1, %0" : "=a" (l_ret) : "dN" (p_port));
return l_ret;
}
 
 
</syntaxhighlight>
 
== The Driver Class Header (Class Definition)==
 
 
<sourcesyntaxhighlight lang="c">
class E1000 : public NetworkDriver
{
private:
uint8_t bar_type; // Type of BOR0BAR0
uint16_t io_base; // IO Base Address
uint64_t mem_base; // MMIO Base Address
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~E1000(); // Default Destructor
};
</syntaxhighlight>
</source>
 
== How the Gears Move (Class methods implementation) ==
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First of all we need to be able to send commands and read results from the NIC. It is important to detect the type of BAR0 and based on that the correct communication mechanism should be adopted. The following two methods encapsulate the read/write commands and uses MMIO or IO ports based on the value in BAR0 which is reflected in bar_type data member flag.
 
<sourcesyntaxhighlight lang="c">
void E1000::writeCommand( uint16_t p_address, uint32_t p_value)
{
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}
}
</syntaxhighlight>
</source>
 
 
Now we need to detect if the card has an EEPROM or not. The Qemu and Bochs emulate EEPROM, but the I217 and 82577LM do not. The following first method tries to read the status field of the EEPROM, the status field should contain the value 0x10, and based on the result the internal data member eerprom_exists. The second method performs a 2-bytes read operation from the EEPROM
 
<sourcesyntaxhighlight lang="c">
bool E1000::detectEEProm()
{
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}
 
</syntaxhighlight>
</source>
 
 
{{You|section=1}}
 
The first thing you will need to do after detecting the BAR0 type and the existence of the EEPROM is to read the hardware MAC address of the NIC. The following method reads the hardware mac address based. If an EEPROM exists it will read it from the EEPROM else it will read it from address 0x5400 where it should be located in that case. It is very important to detect if an EEPROM exists or not prior to reading the MAC address.
 
<sourcesyntaxhighlight lang="c">
 
bool E1000::readMACAddress()
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return true;
}
</syntaxhighlight>
</source>
 
 
Now, we need to configure the transmit and receive descriptor buffers, here are the implementation of the corresponding methods. The rxinit method is identical to the one I use for my e1000 driver. The difference is in txinit
 
<sourcesyntaxhighlight lang="c">
 
void E1000::rxinit()
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writeCommand(REG_RXDESCTAIL, E1000_NUM_RX_DESC-1);
rx_cur = 0;
writeCommand(REG_RCTRL, RCTL_EN| RCTL_SBP| RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_2048RCTL_BSIZE_8192);
}
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</syntaxhighlight>
</source>
 
 
To enable interrupts
<sourcesyntaxhighlight lang="c">
void E1000::enableInterrupt()
{
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}
</syntaxhighlight>
</source>
 
 
As we have defined most of the building blocks and the helper methods lets define the main methods of the class.
 
 
The constructor is responsible for fetching PCI related data and initialize the object internal state
 
<sourcesyntaxhighlight lang="c">
E1000::E1000(PCIConfigHeader * p_pciConfigHeader) : NetworkDriver(p_pciConfigHeader)
{
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eerprom_exists = false;
}
</syntaxhighlight>
</source>
 
The start method basically detects the EEPROM, reads the MAC addresses, setup rx and tx buffers, register the interrupt handler, and enable NIC interrupts
 
 
<sourcesyntaxhighlight lang="c">
 
bool E1000::start ()
Line 443 ⟶ 625:
 
 
</syntaxhighlight>
</source>
 
 
Your interrupt handler should eventually call the fire method which handles the NIC's events
<sourcesyntaxhighlight lang="c">
 
void E1000::fire (InterruptContext * p_interruptContext)
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if ( p_interruptContext->getInteruptNumber() == pciConfigHeader->getIntLine()+IRQ0)
{
/* This might be needed here if your handler doesn't clear interrupts from each device and must be done before EOI if using the PIC.
Without this, the card will spam interrupts as the int-line will stay high. */
writeCommand(REG_IMASK, 0x1);
uint32_t status = readCommand(0xc0);
if(status & 0x04)
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}
 
</syntaxhighlight>
</source>
 
Finally we define the sendPacket method as follows
 
<sourcesyntaxhighlight lang="c">
 
int E1000::sendPacket(const void * p_data, uint16_t p_len)
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tx_descs[tx_cur]->addr = (uint64_t)p_data;
tx_descs[tx_cur]->length = p_len;
tx_descs[tx_cur]->cmd = CMD_EOP | CMD_IFCS | CMD_RS | CMD_RPS;
tx_descs[tx_cur]->status = 0;
uint8_t old_cur = tx_cur;
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}
 
</syntaxhighlight>
</source>
 
 
This is an example of how to instantiate an object of this class and startup you driver. I assume that you have scanned your PCI buses and loaded the found devices parameters into some data structures; in our example this is done by the PCIConfigManager class, which is outside the scope of this tutorial
 
<sourcesyntaxhighlight lang="c">
 
pciConfigHeaderManager.initialize(); // Initialize the PCIConfigHeaderManager Object and scan PCI devices
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}
 
</syntaxhighlight>
</source>
 
 
== Summary and Wrap Up ==
{{You|section=1}}
 
I have presented in this Wiki the steps I followed to make an e1000 driver work with the two e1000e NICs Intel I217 and 82577LM. The wiki does not show how to utilize all the features of the NICs, but basically primitive setup and send/receive packets. Three important issues that I faced:
 
* You need to detect the BAR0 type as some cards uses IO ports and others uses MMIO and you need to communincate with the NIC with the method appropriate to each.
* You need to check if the card supports an EEPROM and read the MAC address from the EEPROM if the card supports it or read it from address 0x5400 if it doedoes snotnot support an EEPROM
* You need to make sure to setup the card TCTRL register (Transmission Control Register) with the value 0b0110000000000111111000011111010. For more details reference the Intel manual for the meaning of the different bits of the register
 
== Manuals ==
These are the full Intel manuals:
[http://www.intel.com/content/www/us/en/ethernet-controllers/ethernet-controller-i217-spec-update.html Intel Ethernet i217 V]
[http://www.intel.com/content/www/us/en/ethernet-controllers/82577-gbe-phy-datasheet.html Intel 82577 Gigabit Ethernet PHY]
 
(Looks like the former manual was moved [http://www.intel.com/content/www/us/en/embedded/products/networking/i217-ethernet-controller-datasheet.html here]).
 
[[Category:Network Hardware]]