Anonymous user
Intel Advanced Encryption Standard New Instructions: Difference between revisions
Intel Advanced Encryption Standard New Instructions (view source)
Revision as of 13:37, 7 June 2024
, 28 days agoReverted edits by Melina148 (talk) to last revision by No92
| [unchecked revision] | [unchecked revision] |
No edit summary |
|||
Line 1:
{{Template:Stub}}
You'll find these instructions on any mid-tier Intel CPU since about 2010 and any AMD CPU since about 2011. Support for these is indicated by checking bit 25 in ecx after calling [[CPUID]] with eax = 0x00000001.
== Overview ==
{| {{wikitable}}
! Instruction
! Description
|-
| <code>AESENC</code> || encrypt a round
|-
| <code>AESENCLAST</code> || encrypt last round
|-
| <code>AESDEC</code> || decrypt a round
|-
| <code>AESDECLAST</code> || decrypt last round
|-
| <code>AESIMC</code> || AES inverse mix columns
|-
| <code>AESKEYGENASSIST</code> || used for key expansion
|}
== See Also ==
=== Articles ===
* [[Wikipedia:AES_instruction_set|AES instruction set]]
=== External Links ===
* [https://software.intel.com/sites/default/files/article/165683/aes-wp-2012-09-22-v01.pdf Intel Paper], including C code samples
* [http://tab.snarc.org/posts/technical/2012-04-12-aes-intrinsics.html A blog post] showing an example implementation using GCC's builtins
| |||