Anonymous user
Instruction Set Architecture: Difference between revisions
no edit summary
[unchecked revision] | [unchecked revision] |
m (→One Instruction Set: Some language polish + never use <br> in prose when you don't know the rendered width relative to the font) |
No edit summary |
||
(2 intermediate revisions by 2 users not shown) | |||
Line 1:
{{stub}}
This page is intended to provide an explanation of some of the various
See also [[Historical Notes on CISC and RISC]].
==Church-Turing Thesis==
To be
Common algorithms:
*Logic functions: One might not notice, but e.g. brains use in daily challenges for decisions simple state machines and every state machine can be expressed by logic functions.
Line 15:
As you might have noticed everything can be implemented by logic functions. This is important: To be able to do any logic function means to be Church-Turing mighty.
To be exact, only a single logic function, such as [[wikipedia:Sheffer stroke|NAND]], with two inputs and one output is needed. Other sets of "complete" logic functions can be found, but NAND is the most common.
Any Instruction Set Architecture (ISA) is Church-Turing mighty.
Line 21:
==Flynn's Bottleneck and Fisher's Optimism==
M. J. Flynn (*1934) found, in 1970, a very interesting fact: If one fetches (loads) only one instruction per cycle, one will never get more than one executed instruction per cycle. (This is valid for each physical ALU.)<br>
J. A. Fisher (*1946) argued in 1984 that an array (packed) data structure could achieve more executed instructions per cycle than one.<br>
This will become important speaking when about RISC/CISC dis-/advantages.
==One Instruction Set==
The so called Ultimate Reduced Instruction Set Computer (URISC) or One Instruction Set Computer (OISC) is programmed by only one instruction. This instruction must make it possible to decide, to move data, to calculate, and to jump to different targets in the instruction stream. This is only possible with a complex instruction.
Applications for a computer programmed by this ISA have huge
==Minimal Instruction Set==
It is defined by less than 32 instructions (one can't really distinguish between MISC and RISC). Mostly, MISCs are Stack machines. Owing to missing security features and the huge
==Reduced Instruction Set==
A RISC provides fast and simple basic instructions, e.g. conditional jumps, logic functions, addition/subtraction, multiplication/division, etc. It's execution environment is simple, because RISC must not provide complex instructions. This
==Complex Instruction Set==
A CISC instantiates simple and additional complex instructions. It comes mostly with different execution environments and security features. Especially streaming extensions like SSE must be named.
They are the reason why RISC-only processors almost disappeared nowadays. Flynn's bottleneck applies, but by using streaming extensions the chance to reduce its influence and switch to Fisher's optimism grows fast. Other advanced features may reduce memory
==Hybrid Instruction Set==
Modern CPUs are built upon a hybrid RISC-CISC architecture. RISC processors can be built more easily and clocked faster, but lack the advanced instructions of a CISC. To get the best of both worlds, a hybrid is built. A RISC is used as the ALU, and is wrapped by a CISC environment. Any instruction is interpreted by this CISC and is split into one or more sub-instructions, called "micro-opcodes", for the RISC. Additionally, the CISC-wrapping provides security, along with operating system stability and control. Nowadays, only microcontrollers use pure RISC; any other CPU is more or less a hybrid RISC-CISC CPU.
[[Category:Instruction Set Architecture]]
|