ISA DMA: Difference between revisions

ISA DMA (view source)

Revision as of 00:01, 26 October 2008

58 bytes removed , 15 years ago

→‎DMA Genesis. Chapter 1, Verse 1: Let's just say that the EISA and PS/2 DMA controllers died with EISA and MCA itself.

[unchecked revision]

VisualWikitext

Anonymous user

osdev>Yuhong

Revision as of 20:16, 16 February 2008 (view source) osdev>Pietro10 No edit summary ← Older edit		Revision as of 00:01, 26 October 2008 (view source) osdev>Yuhong (→‎DMA Genesis. Chapter 1, Verse 1: Let's just say that the EISA and PS/2 DMA controllers died with EISA and MCA itself.) Newer edit →
Line 20: Previously it was mentioned that the DMA controller is able to signal completion and even ask for more information. Unfortunately this would make expansion slots too big, so IBM left all of the connections to the DMA chips off. The only time you know when a transfer is complete is for a peripheral to signal an interrupt. This implies that all peripherals using a DMA channel are limited to no more than 64/128 KB transfers for fear of upsetting the DMA controller. Finally, *ALL* DMA controllers run at 4Mhz. (Information taken from ISA Specification) *NO EXCEPTIONS*. Ignore that Ghz tag on your processor or the fact that even PCI runs at 33MHZ. DMA controllers are fixed at this rate. This includes EISA and PS/2 32-bit DMA controllers. The only ~~real difference~~differences between these and the stock ISA DMA controllers is a extra page register allowing for 64k transfers anywhere in 4GBytes of space and the ability to do 32-bit transfers, and these DMA controllers exists only on EISA and MCA systems, which are now obsolete and are not described here. (before you say, "But weren't these 32-bit transfer capable?" please show me an emulator that supports native 32-bit EISA DMA transactions. ISA DMA is almost irrelevant enough, EISA DMA is almost vapourware) So after reading all the above the main point are