|
;The main points about ISA DMA are:
'''ISA DMA''' ('''Industry Standard Architecture Direct Memory Access''') in today's PC architecture, like ISA itself, is in many ways like an appendix. It is used by the floppy disk controller, ISA sound cards, ISA network cards and parallel ports (if they support ECP mode). Whilst interrupt, keyboard and timer interface circuits have obvious and relevant uses, the ISA DMA controller and it's programming interface are still well and truly stuck in the 1970's where they were first designed. Modern PCI controllers typically have their own 'bus mastering', which is far better.
* ISA DMA is not the same thing as PCI Busmastering DMA;
* ISA DMA channels 1, 2 and 3 are available for 8 bit transfers to ISA peripherals;
* ISA DMA channels 5, 6 and 7 are available for 16 bit transfers to ISA peripherals;
* Transfers must not cross physical 64 KB boundaries and must never be bigger than 64 KB;
* Transfers must be physically contiguous, and can only target the lowest 16 MB of physical memory;
* ISA DMA is slow - theoretically 4.77 MB/second, but more like 400 KB/second due to ISA bus protocols;
* ISA DMA frees up CPU resources, but adds an extremely heavy load to the memory bus;
* Very few devices currently use ISA DMA -- only internal floppies, some embedded sound chips, some parallel ports, and some serial ports.
Notes:
The idea behind DMA is that you can set up a 'channel' with an address pointing into memory and the length of the data to be transferred. Once set up, you can tell the peripheral owning the 'channel' to do whatever it is supposed to do (e.g. read a sector). Then the CPU can go onto something else. Periodically when the data bus isn't being used by the CPU the DMA chip takes over and transfers data between the peripheral and memory without involving the CPU. When the transfer is complete (e.g. an entire sector has been sent to the floppy drive) the DMA chip will than signal that it is finished. The DMA chip can even signal if it has run out of data, allowing the CPU to program some new information and another transaction to proceed.
* Sound Blaster and Sound Blaster PRO only support 8 bit DMA;
DMA can improve the speed of a system quite a bit and was borrowed by Intel (who designed the DMA controller chip) from the old 1960's mainframes which had DMA channels for all devices (CPU's weren't all on a single chip and very slow back then).
* [[Sound Blaster 16]]+ supports both;
* [[Floppy disk controllers]] only support 8 bit DMA and are hardwired to use DMA Channel 2.
== There Is More Than One Kind of DMA on a PC ==
Of course all good ideas can have downsides and while Intel can't really be blamed for what is about to be described, IBM certainly can.
Modern PCI controllers always have their own 'Busmastering DMA', which is far better than ISA DMA. Even USB floppy drives send their DMA
data using PCI Busmastering, through the PCI USB controller.
PCI Busmasters can access memory with 32 bit addressing. Newer PCI cards are starting to support 64 bit addressing (although at the moment most
don't). Typically PCI cards use 'scatter-gather' bus mastering, where one page is used as a directory of data pages. This almost completely overcomes
the "physical memory only" limitation of all forms of DMA.
== DMA Genesis, Chapter 1, Verse 1 ==
In the beginning there was a PC, but the PC was slow. IBM looked down from the heavens and said "Slap on a DMA controller - that should speed it up." IBM's heart was in the right place, its collective brains were elsewhere as the DMA controller never met the needs of the system. The PC/AT standard contains 2 Intel 8237A DMA chips, connected as Master/Slave. The second chip is Master, and its first line (Channel 4) is used by the first chip, which is Slave. (This is unlike the interrupt controller, where the first chip is Master.) The 8237A was designed for the old 8080 8-bit processor and this is probably the main reason for so many DMA problems. 8088 and 8086 processors chosen by IBM for its PC were too advanced for the DMA controller.
== ISA DMA Background ==
Each 8237 DMA chip has 4 DMA channels. DMA0-DMA3 on the first chip and DMA4-DMA7 on the second. The first DMA controller is wired up for 8 bit transfers, while the second is wired up for 16 bit transfers.
'''ISA DMA''' (''Industry Standard Architecture Direct Memory Access''), like ISA itself, is an [https://en.wikipedia.org/wiki/Appendix_(anatomy) appendix] for modern PCs. It is used by the
internal floppy disk controller, ISA sound cards, ISA network cards, and parallel ports (if they support ECP mode). Whilst interrupt, keyboard
and timer interface circuits have obvious and relevant uses, the ISA DMA controller and its programming interface are still well and truly stuck in the
1970s where they were first designed.
The idea behind DMA is that you can set up a 'channel' with an address pointing into memory and the length of the data to be transferred. Once set up, the
DMA Channel 0 is unavailable as it was used for memory refresh, and remains reserved because of this (even though modern computers don't use it). DMA channel 4 cannot be used for peripherals because it is used for cascading the other DMA controller.
CPU can tell the peripheral owning the channel to do whatever it is supposed to do (e.g. read a sector). Then the CPU can go do something else.
When the memory bus isn't being used by the CPU, the DMA chip takes over and transfers data between the peripheral and memory without involving the CPU. When
the transfer is complete (e.g. an entire sector has been sent to the floppy drive) the DMA chip then signals that it is finished. The DMA chip can even
signal if it has run out of data, allowing the system to locate the next block of data to transfer on the same DMA transaction.
DMA can improve the speed of a system quite a bit and was borrowed by Intel (who designed the DMA controller chip) from the old 1960s mainframes which had
DMA channels for all devices (CPUs weren't all on a single chip and very slow back then).
Of course all good ideas can have downsides and while Intel can't really be blamed for what is about to be described, IBM certainly can.
DMA Channels 1, 2 and 3 can only transfer 64 KB of information at a time (the internal registers are only 16 bit). In order to extend this, IBM added an ''external'' page register allowing access to 16 MB of memory (24 bits total). If a DMA transfer crosses a 64 KB boundary, the internal count register wraps around to zero, the external page register is ''not'' incremented. The DMA controller will happily provide the peripheral attached with whatever it finds at the new address. As a rule 8 bit DMA transfers must not cross 64 KB boundaries and must never be bigger than 64 KB.
In the beginning there was a PC, but the PC was slow. IBM looked down from the heavens and said "Slap on a DMA controller -- that should speed it up." IBM's
DMA Channels 5, 6 and 7 transfer data 16 bits at a time, by shifting addresses one bit to the right and clearing the lower bit. The addressing is exactly the same except you can now start on 128 KB boundaries and transfer up to 128 KB of information at a time before the DMA boldly transfers what has never been transferred before...
heart was in the right place; its collective brains were elsewhere as the DMA controller never met the needs of the system. The PC/AT standard contains 2
Intel 8237A DMA chips, connected as Master/Slave. The second chip is Master, and its first line (Channel 4) is used by the first chip, which is Slave. (This
is unlike the interrupt controller, where the first chip is Master.) The 8237A was designed for the old 8080 8-bit processor and this is probably the main
reason for so many DMA problems. The 8088 and 8086 processors chosen by IBM for its PC were too advanced for the DMA controller.
Previously it was mentioned that thea DMA controller is able to signal completion and even ask for more information. Unfortunately this would make expansion slots too big, so IBM left all of the connections to the DMA chips off. The only time you know when a transfer is complete is for a peripheral to signal an interrupt. This implies that all peripherals using a DMA channel are limited to no more than 64/128 KB transfers for fear of upsetting the DMA controller.
slots too big, so IBM left all of the connections to the DMA chips off. The only time you know when a transfer is complete is for a peripheral to signal an
interrupt. This implies that all peripherals using an ISA DMA channel are limited to no more than 64 KB transfers for fear of upsetting the DMA controller.
Even with the PC/AT, IBM began bypassing the ISA DMA used in the PC/XT and used [[ATA PIO Mode]] for the hard disk. This
Finally, '''all''' DMA controllers run at 4 MHz. (Information taken from ISA Specification) '''No exceptions'''.
was because of the 64 KB limitations outlined above and the fact that the 286 processor could perform 16 bit transactions at 6 MHz. Even the ISA bus could
Ignore that GHz tag on your processor or the fact that even PCI runs at 33 MHz. DMA controllers are fixed at this rate. This includes EISA and PS/2 32-bit DMA controllers. Some of the differences between these and the stock ISA DMA controllers is a extra page register allowing for 64k transfers anywhere in 4 GiB of space and the ability to do 32-bit transfers, and these DMA controllers exists only on EISA and MCA systems, which are now obsolete and are not described here.
run at a speed of up to 12 MHz, far faster than the 4.77 MHz the DMA controller was running at.
Expansion card designers were also upset with DMA's lack of capabilities, noticeably 'Hard-Card' hard disk expansion card manufacturers who depended on the
So after reading all the above, the main points are:
speed of data transfer.
* DMA channel 1, 2 and 3 are for 8 bit transfers;
* DMA channel 5, 6 and 7 are 16 bit transfers;
* Transfers shouldn't cross 64 KB or 128 KB boundaries;
* Transfers can only be from the lowest 16 MB of memory;
* DMA is slow - theoretically 4 MB/second but more like 500 KB/second due to ISA bus protocols.
To get around the limitations of the 'on board' DMA controller, expansion card manufacturers began to put their own DMA controllers on their expansion
Note that:
cards. They functioned exactly the same way as the 'on board' DMA, 'stealing memory bus cycles' when the processor wasn't looking and thus improving the
* Sound Blaster and Sound Blaster PRO only support 8 bit DMA;
performance of the system as a whole. These "ISA Bus Masters" are still usually limited to the lower 16 MiB of memory, but do not have the 4.77 MHz issue.
* Sound Blaster 16+ supports both;
This trend continued through the creation of the PCI bus, which eventually entirely replaced the ISA bus in PCs.
* Floppy disk controllers only support 8 bit DMA and usually use DMA Channel 2.
== Technical Details ==
Each 8237 DMA chip has 4 DMA channels. DMA0-DMA3 on the first chip and DMA4-DMA7 on the second. The first DMA controller is wired up for 8 bit transfers,
while the second is wired up for 16 bit transfers. On some tutorials or other wiki articles, you will sometimes see the '''second''' DMA chip (channels 4 to 7) labeled as the "'''master'''" controller, and the first (channels 0 to 3) called the "slave". This is highly confusing, and these terms will not be used again, here.
DMA Channel 0 is unavailable as it was used for a short time for DRAM memory refresh, and remains reserved because of this (even though modern computers
don't use it). DMA channel 4 cannot be used for peripherals because it is used for cascading the other DMA controller.
The internal address registers of the DMA controller are only 16 bits. In order to extend this, IBM added one ''external'' "page register" byte per channel,
allowing access to 16 MB of memory (24 bits total). If a DMA transfer crosses a 64 KB boundary, the internal address register wraps around to zero,
and the external page register is '''not''' incremented. The DMA controller will happily continue the transfer with whatever data it finds at
the new address.
ISA-based DMA controllers are specified to run at 4.77 MHz. '''No exceptions'''. If the "front-side" (memory) bus of a system runs at 133 MHz, it will be
== Busmaster DMA ==
artificially slowed down to 4.77 MHz when transferring each ISA DMA byte/word. This includes EISA and PS/2 32-bit
controllers, even though these controllers have an extra page register (which allows a 4 GiB addressing space)
and the ability to do 32 bit transfers. (These DMA controllers exist only on EISA and MCA systems, which are now obsolete and are not further
described here.)
The IBM/XT used DMA channel 3 for hard disk connections but instead of using DMA the IBM/AT used direct writing to the hard disk using the processor, this was because of the 128 KB limitations outlined above and the fact that the 286 processor could perform 16 bit transactions at 6 MHz. Even the ISA bus could run at a speed of up to 12 MHz, far faster than the 4.77 MHz the DMA controller was running at.
== Programming Details ==
Expansion card designers were also upset with DMA's lack of capabilities, noticeably 'Hard-Card' hard disk expansion card manufacturers who depended on the speed of data transfer.
=== 16 bit issues ===
To get around the limitations of the 'on board' DMA controller, expansion card manufacturers began to put their own DMA controllers on their expansion cards. The controllers didn't have any of the design 'features' of the 8237A and could address all 16 MiB of ISA addressable memory with the full 16 bit data bus width. They functioned exactly the same way as the 'on board' DMA, 'stealing bus cycles' when the processor wasn't looking and thus improving the performance of the system as a whole.
The 16 bit channels (5, 6, and 7) have a special addressing scheme to handle the way they increment addresses. The internal registers increment by 1,
but the memory address needs to be incremented by 2 between each access. The solution is that the "start address" that the CPU stores in the DMA controller
needs to be shifted right by 1 bit. On each memory access, this internal 16 bit address value is incremented by one, then that value is taken and shifted
one bit to the left (clearing the lower bit) before being used as an address. The external "page register" addressing byte is then appended in the normal
way. It is important to note that the upper bit of the internal address is '''lost''' when it is shifted left -- it is not ORed into the page register byte.
This prevents DMA transfers bigger than 64 KB from working even though they should be technically possible for 16 bit channels, because the address register
will effectively wrap around to zero without incrementing the page register byte.
=== Physical Memory vs. Paging ===
Busmaster DMA is probably easier to understand than normal DMA. Provided you know what registers are on your expansion card, you can send them the address and the amount of data to transfer. The expansion card will send you an interrupt upon completion.
Paged memory mapping is exclusively controlled by the CPU. The whole point of DMA is to bypass the CPU. Therefore, no DMA can ever access any virtual
PCI Bus Masters can of course access memory with 32 bit addressing. Newer PCI cards are starting to support 64 bit addressing (although at the moment most don't). Typically PCI cards use 'scatter-gather' bus mastering, where one page is used as a directory of data pages. This is makes them especially suitable for paging operating systems (where contiguous pages are rare).
memory addresses. All DMA is always done on physical memory addresses only. ISA DMA has a 16 MB physical address limit.
Since DMA runs independently of the CPU, it is important that an OS allocates a block of contiguous physical memory for the DMA transfer in
ISA Bus Masters are still limited to the lower 16 MiB of memory - this is an ISA limitation.
a way that prevents that memory from being used for any other purpose, or swapped out, until the DMA transfer is complete.
Note: VM86 mode does not use ''physical'' addressing. The memory addresses are ''fake''. In VM86 mode the OS must emulate any DMA transactions on
== Programming the PC DMA controllers ==
behalf of an application.
=== PagingBuffer Size ===
A typical 1.44 MB floppy disk can easily transfer 36 sectors of data in a single transfer. This is only 18 KB. The biggest internal floppy with
worst-case formatting may be able to transfer 84 sectors at once. This is still only 42 KB. A Soundblaster card may run best with a 64 KB buffer. It
is never necessary to try to double-buffer ISA DMA transfers, because they are so slow anyway. There are at most 6 usable DMA channels, and it is not
necessary to allocate a full 64 KB to each of them. Putting all of this together, any OS should be easily able to allocate all the ISA DMA physical
memory that it needs from a 256 KB pool, or even only half of that.
=== The Flip-Flop ===
As this article assumes you are writing your own OS, the subject of memory management is very important unless you are writing a 286 based operating system. This is because as mentioned earlier, all DMA transactions must occur in the lower 16 MiB of memory. (Yes, I'm repeating myself - memorize - it is crucial.)
Many devices on a PC (e.g. ATA disk drives) use 8 bit IO Ports to receive 16 bit values. This is done using a flip-flop. The device expects the low
byte first. As soon as it receives a byte, the flip-flop changes state and then the device expects the high byte. When the high byte is received,
the flip-flop changes state again, and the device expects a new low byte. Usually, each 16 bit 'register' will have its own flip-flop, but the ISA
DMA controller has a problem regarding this.
On a 8237 chip, there is '''only one''' flip-flop. And there are eight of the 16 bit registers. And there can be up to three device drivers all competing
To be more specific all DMA transactions must occur in ''physical memory''. The DMA controller only functions with ''physical'' memory, if you pass it a virtual address happily mapped into anywhere in memory, the DMA controller will happily ignore your carefully constructed page mapping and access whatever it decides to. VM86 mode does not use ''physical'' addressing. The physical addresses are ''fake''. In VM86 mode the OS must emulate any DMA transactions on behalf of an application, probably in a totally non-DMA way. Almost all DOS memory managers and operating systems that uses V86 mode to run DOS applications (including Windows 3.x enhanced mode and EMM386) supply virtual DMA functions, but these are basically the same, the V86 monitor 'fakes' the DMA transaction. DMA has no knowledge of paging whatsoever and I should point out that this includes Bus Master DMA.
for the use of that one flip-flop simultaneously.
This creates two serious problems. One is "contention issues". The other is that it is difficult to be sure what state the flip-flop is currently in.
Finally (and this is a great laugh when it happens) don't forget to 'pin' the pages in memory. Imagine the floppy drive trying to read data from memory and you swap that data out to the hard drive. The DMA chip doesn't know -
The standard solution for dealing with the flip-flop state issue is to reset the flip-flop to "low byte" state every single time you want to use it, just
"Paging? Whats that then? Dunno. You've just mapped in the password file? No problem, I'll write that out to the floppy instead."
so you can be certain it is in the proper state before sending bytes. There are only two solutions to "contention": either use a [[lock]], or allow only
DMA memory is like Memory Mapped I/O - do not move - do not page.
one ISA DMA driver, so that contention is impossible.
(I apologise for sounding really dictatorial, it's just that DMA is so easy to screw up. Lots' more things to screw up later! - just wait till we get to commands)
=== Masking DRQ ===
One way to handle this situation is to manage memory below 16 MB using a 'bitmap' so that contiguous pages that don't cross 64 KB or 128 KB boundaries can be found, and use free page stacks (or anything else) for memory above 16 MB.
Setting up a DMA transfer always requires setting up both "ends" of the transfer. That is, whichever peripheral owns the DMA channel needs to be told
to transfer a block of data via DMA. And the DMA controller needs to be told the memory address, the transfer length, perhaps a transfer "mode", and
a transfer direction (read or write). So, one of these two things always needs to be done ''first'' -- and it is usually the peripheral that has a long
latency time before being ready to transfer the first byte. If you set up the peripheral first, however, its first DMA request signal (often called
DRQ) may arrive while you are in the middle of setting up the DMA controller.
The answer is to mask DRQ for a particular channel while you are initializing the DMA controller. There are three ways of temporarily disabling channels
An example for getting it right:
described below.
* When your OS starts it detects (or is told of) a device requiring DMA memory.
* Map the lowest 64K of ''physical'' memory elsewhere in memory and aim the DMA channel you are setting up at address 0.
* Set up the DMA channel for the correct type of transaction (more on this later).
=== Transfer Length ===
* Next DMA Channel, map the next 64K of ''physical'' memory somewhere, aim your DMA channel at address 64K.
The value that gets stored into each Count Register is always the transfer length (either bytes or words) '''minus 1'''. If you forget to subtract
* Set up the DMA channel for the correct type of transaction (more on this later).
the one, you will get an error on your transfer.
=== Interrupt on Completion ===
* Complete building your pages stacks / bitmaps whatever and add any lower memory left over.
As implemented in a PC, the DMA controller can not send interrupts. Hopefully, whichever peripheral "owns" each DMA channel will send the CPU an
interrupt when a transfer completes. However, some peripherals may '''not''' send an interrupt if a transfer fails with an error. As always, timeouts
are important.
=== The Registers ===
Apart from making sure that you have a copy somewhere of the information in the first 4K of memory and the Extended BIOS Data Area (these are for VM86 tasks if you decide to add BIOS/DOS/VESA/PCI support later), the above example will allow you to have a flat paged memory area from 0 to forever while still allowing you OS to use old DMA dependent peripherals. The device drivers work with CPU paged memory areas, while the DMA controller is happily working with low memory ''under 16 MiB''. Have the driver write data to the paging relocated area, send commands to the peripheral and the DMA chip will access ''physical'' memory correctly when asked to do so.
The master and slave DMA controllers are very similar, so (to save space) both of them have been combined into the following table. Please try
not to let this confuse you.
Note: for Address and Count Registers on channels 5 to 7, see [[#16 bit issues|16 bit issues]] above.
Each 8237A has 18 registers, addressed via the I/O Port bus:
===Registers===
Each 8237A has 5 registers, addressed via I/O space:
{| {{wikitable}}
|-
!Channels 0-3
!8237A No. 1
!Channels 4-7
!8237A No. 2
|
|
|
|-
!IO Port
!Address
!IO Port
!Address
!Size
!Read or Write
!Function
|-
|0x00
|0xC0
|Word
|W
|Start Address Register channel 0/4 (unusable)
|-
|0x01
|0xC2
|Word
|W
|Count Register channel 0/4 (unusable)
|-
|0x02
|0xC4
|Word
|W
|Start Address Register channel 1/5
|-
|0x03
|0xC6
|Word
|W
|Count Register channel 1/5
|-
|0x04
|0xC8
|Word
|W
|Start Address Register channel 2/6
|-
|0x05
|0xCA
|Word
|W
|Count Register channel 2/6
|-
|0x06
|0xCC
|Word
|W
|Start Address Register channel 3/7
|-
|0x07
|0xCE
|Word
|W
|Count Register channel 3/7
|-
|0x08
|0xD0
|Byte
|R
|Status Register
|0x08
|0xD0
|Byte
|W
|Command Register
|0x09
|0xD2
|Byte
|W
|Request Register
|0x0A
|0xD4
|Byte
|W
|DMASingle Channel Mask Register
|-
|0x0B
|0xD6
|Byte
|W
|DMA Mode Register
|-
|0x0C
|0xD8
|Byte
|R
|W
|Byte / Word Register
|Flip-Flop Reset Register
|-
|0x0D
|0xDA
|Byte
|R
|Intermediate Register
|-
|0x0D
|0xDA
|Byte
|W
|Master Reset Register
|-
|0x0E
|0xDC
|Byte
|W
|Mask Reset Register
|-
|0x0F
|0xDE
|Byte
|W
|RW
|DMA Mask Register
|MultiChannel Mask Register (reading is undocumented, but it works!)
|-
|}
Each DMA Channel also has an Externalexternal R/W Page Address Register that is added tocontains the upper 8 bits of the DMA24 bit transfer memory address:
{| {{wikitable}}
|-
|0x87
|DMA Channel 0 Page Address Register (bits A17 - A24unusable)
|-
|0x83
|DMA Channel 1 Page Address Register (bits A17 - A24)
|-
|0x81
|Channel 2 Page Address Register
|-
|0x82
|DMA Channel 23 Page Address Register (bits A17 - A24)
|-
|0x81
|DMA Channel 3 Page Address Register (bits A17 - A24)
|-
|0x8F
|DMA Channel 4 Page Address Register (bits A17 - A24unusable)
|-
|0x8B
|DMA Channel 5 Page Address Register (bits A17 - A24)
|-
|0x89
|DMA Channel 6 Page Address Register (bits A17 - A24)
|-
|0x8A
|DMA Channel 7 Page Address Register (bits A17 - A24)
|-
|}
==== Useful Registers ====
(Bit Patterns from Indispensable PC Hardware Book - I'm commenting the useful parts i.e. the bits you can actually use, a lot of the 'features' of the 8237 do not function in the PC and the fact they do not work introduces new 'features'. Please assume that if anything isn't explicitly mentioned, it implicitly does not function. Messing with things not mentioned will usually result in screwing up of your computer. Don't take my word for it (I could be Kermit the Frog for all you know!) so feel free to ask other people and do whatever makes you feel good.)
;Status Registers 0x08 and 0xD0 (Read)
{| {{wikitable}}
|-
|Bit 7
|Bit 6
|Bit 5
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|REQ3
|REQ2
|REQ1
|REQ0
|TC3
|TC2
|TC1
|TC0
|}
* '''REQ3-0''': When set: DMA Request Pending.
* '''TC3-0''': When set: Transfer Complete.
This register isn't very important in light of the fact that the 8237 can't send an IRQ to tell you that it has finished. Usually there is no need to poll this register as again the peripheral owner will send an interrupt when a transaction has finished and polling would be a total waste of time.
;Command Registers 0x08 and 0xD0 (Write)
{| {{wikitable}}
|-
|Bit 7
|Bit 6
|Bit 5
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|DACKP
|DRQP
|EXTW
|PRIO
|COMP
|COND
|ADHE
|MMT
|}
This register really shows how incompatible the 8237 is with the PC hardware.
* Let's start with EXTW and COMP. These increase the speed of DMA transfer by 25% be removing one of the clock cycles. Does it work? No.
* PRIO. When zeroed, this allows DMA priorities to be rotated allowing freedom and liberty for all peripherals that share the data bus. Does it work? No.
* MMT and ADHE. Did you know that the IBM PC could do memory to memory transfers since 1981? Thats right, hardware sprites, hardware frame buffering from one location to another. Does it work? No.
* COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This lets you set up multiple DMA channels without masking each and every channel.
;Request Registers 0x09 and 0xD2 (Write)
Used for memory to memory transfers and setting up priority rotation- absolutely useless.
;DMA Channel Mask Registers 0x0A and 0xD4 (Write)
;Single Channel Mask Registers 0x0A and 0xD4 (Write)
{| {{wikitable}}
|-
|
|
|MASK_ON
|STCL
|SEL 1
|SEL1
|SEL 0
|}
To mask a channel for programming/whatever set STCL to 1 and SEL0 and SEL1 to select the channel to be masked.
* Sending 0x4(100b) would mask DMA Channel 0 of the appropriate 8237.
* Sending 0x0(000b) would unmask DMA Channel 0 of the appropriate 8237.
* To unmask a channel set STCL to 0.
This register only allows you to mask/unmask a '''single''' DMA channel. If you need to mask multiple DMA channels, you need to use the following:
These registers are used to mask (or unmask) DRQ for a single channel only, on either the master or slave DMA chip.
;DMA Mask Registers 0x0F and 0xDE (Write)
That is, if you do not want to figure out the mask states of all the other channels, you can mask/unmask DRQ for one channel at a time.
Use the SEL 0 and 1 bits to select the channel, and the MASK_ON bit to set or clear masking for it.
Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.
;MultiChannel Mask Registers 0x0F and 0xDE (Read and Write)
{| {{wikitable}}
|-
|
|
|MASK3
|STC3
|MASK2
|STC2
|MASK1
|STC1
|MASK0
|STC0
|}
Setting the appropriate bits to 0 or 1 allows you to maskunmask or unmaskmask (respectively) DRQ for those channels. DMAUsing channelsthis 3,register 2, 1, 0 or 7, 6, 5, 4. Notemeans that maskingyour DMAdriver channel 4 will mask 7, 6, 5 and 4 due to cascading.needs
to know the desired mask states of ''all'' the channels at that moment. There are several ways to do this, but one is simply to read this register, first.
Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.
;DMA Mode Registers 0x0B and 0xD6 (Write)
|MOD1
|MOD0
|DOWN
|IDEC
|AUTO
|TRA1
|}
ThisSetting this register is a little tricky as it depends highly on the peripheral you are programming the DMA controller for. However, the
driver for the peripheral is the entity that needs to set this register, and it should know what mode the peripheral needs.
* '''SEL0''' and '''SEL1''' select the channel you want to change;
* '''TRA0''' and '''TRA1''' selects the transfer type;
** 0b00 runs a self test of the controller;
** 0b01 DMA ChannelPeripheral is for writing to memory;
** 0b10 DMA ChannelPeripheral is for reading from memory;
** 0b11 invalid.
* '''AUTO''': When this bit is set, after a transfer has completed the channel resets itself to the address and count values you programmed into it. This is great for floppy transfers. Read in a track - the values set themselves up for reading again immediately. For writing you'd only need to alter the transfer mode - not the addresses. Some expansion cards do not support auto-init DMA such as Sound Blaster 1.x. These devices will crash if used with auto-init DMA. Sound Blaster 2.0 and later do support auto-init DMA.
* '''DOWN''': Reverses the memory order of the data, when set. Memory is accessed from high addresses down to low addresses (the address is decremented between each transfer).
* '''IDEC''': Increment/Decrement. I guess if you wanted to write big endian data to a floppy drive you could. Big-endian processor based computers wouldn't be using an 8237.
* '''MOD0''' and '''MOD1''': This is where some problems can arise based on the peripheral the DMA controller is attached to. The DMA controller has several modes:
** 0b00 = Transfer on Demand;
** 0b11 = Cascade Mode (use to cascade another DMA controller).
Single transfer mode is good for peripherals than cannot cache a lot of data at once. A good example is early floppy controllers that have only a very small buffer. The DMA controller and CPU can share the data bus happily. Sound Blaster and Sound Blaster Pro use software or Single Transfer DMA Mode.
Non-82077AA Floppy controllers, Sound Blaster, and Sound Blaster Pro should use Single Transfer DMA Mode.
Block transfer mode is good for peripherals that can buffer entire blocks of information. A goodAn example of this is ana ESDIhard or SCSIdisk controller without Bus Master DMAboard.
Demand transfer mode is good for peripherals that start and stop intermittently such as a tape drive. The drive can read a whole load of information for as long as it can and the suspend the transfer to move to another section of the tape. Newer floppy controllers also work well with demand transfer because they have FIFO buffers to store information being read and written. The peripheral controls the flow, and as the information flow is uninterrupted, performance can be gained. CPU's in these later computers generally have caches and can continue working uninterrupted during a demand DMA transfer. Older computers will slow down as their CPU's wait for the data bus to become available.
long as it can and the suspend the transfer to move to another section of the tape. Newer floppy controllers also work well with demand transfer because
they have FIFO buffers to store information being read and written (but you need to set up the FIFO properly). The peripheral controls the flow, and as
the information flow is uninterrupted, performance can be gained. CPUs in these later computers generally have caches and can continue working
uninterrupted during a demand DMA transfer. Older computers will slow down as their CPUs wait for the memory bus to become available.
;Flip-Flop Reset Registers 0x0C and 0xD8 (Write)
In addition to the above registers the 8237 has three command registers:
;Master Reset Registers 0x0D and 0xDA (Write)
;Mask Reset Registers 0x0E and 0xDC (Write)
Send any value to the Reset registers to activate them.
The first command register is 0xd8 which is called the 'reset flip-flop' register. The DMA controller is an 8-bit chip. In order to write 16-bit values into an address register or count register you must write two 8 bit values appropriate register address (to follow). Imagine however that you only write one 8 bit value and the the next time try to write a 16 bit value. The DMA chip will be expecting the high byte, not the low byte. Clearing the flip-flop guarantees getting the address into the DMA controller in the right order. To reset the flip-flop write anything to the register :
Master Reset sets Flip-Flop low, clears Status, and sets all Mask bits ON.
Mask Reset sets all Mask bits OFF.
The following statement from the previous wiki article needs to be verified on real hardware, because it is likely to be wrong: "The Reset Flip-Flop command
;ASM
must be sent ''before any'' 16 bit transaction. The flip-flop ''does not reset'' after the DMA controller has received the second byte."
out 0xd8, 0xFF
;C
<pre>
void reset_flipflop_DMA()
{
outb(0xd8, 0xFF);
}
</pre>
==== The Other Registers ====
Another dictate - the reset flip-flop command must be sent ''before any'' 16 bit transaction. The flip-flop ''does not reset'' after the DMA controller has received the second byte. Easily missed, can cause many problems.
;Status Registers 0x08 and 0xD0 (Read)
The second command register is the 'master reset and clear'. Writing anything to this register (0x0d) resets all count, address and mask values ready for you to program.
;ASM
out 0x0d, 0xFF
;reinitialize all DMA channels now
;C
<pre>
void hard_reset_DMA()
{
outb(0x0d, 0xFF);
}
</pre>
The third command register is the 'clear mask register'. Writing anything to this register (0xDC) will clear the mask register (wow!) releasing all DMA channels to accept DMA requests.
;ASM
out 0xdc, 0xFF
; reinitialize all DMA channels now
;C
<pre>
void unmask_all_DMA()
{
outb(0xdc, 0xFF);
}
</pre>
== Address and Count Registers ==
Each DMA chip has 4 16-bit address registers, 4 16-bit count registers and 4 ''external'' 8-bit page registers.
As previously mentioned a DMA controller ''cannot'' address or transfer more than 65536 bytes or words of information at a time.
The page registers can allow access to the lower 16 MiB of memory but are ''not'' incremented when crossing a 64k boundary. The easiest way is to make sure the address you supply in the address register is ''zero'' and that any addressing that you program the DMA controller to do is done using the external page register. It seems stupid, but unless you know that your transfer will not be over 64k it is the safest.
Example page register settings:
{| {{wikitable}}
! Page register
! Physical address
!
|-
|Bit 07
|Bit 06
|Bit 5
|
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|REQ3
| 1
|REQ2
| 0x10000
|REQ1
| (64k)
|REQ0
|-
| 2TC3
|TC2
| 0x20000
|TC1
| (128k)
|-TC0
| .
| .
|
|-
| .
| .
|
|-
| .
| .
|
|-
| etc...
| etc...
|
|}
* REQ3-0: When set: DMA Request Pending.
Make sure that you map the ''physical address'' of your DMA buffer somewhere in memory if using paging. This buffer can ''then'' be referred to by it's virtual memory address. Mark the memory as non pageable. Even though it's not memory mapped I/O, it is, except that isn't. Think of it as borrowing memory from the system because the expansion card manufacturer was too stingy to supply adequate buffering memory on their card.
* TC3-0: When set: Transfer Complete.
* Reading this register will clear the TC bits.
This register isn't very important in light of the fact that the 8237 can't send an IRQ to tell you that it has finished. Usually there is no need to poll
OK, the I/O port addresses:
this register as the peripheral (at the other end of the DMA) will send an interrupt when a transaction has completed.
{| {{wikitable}}
! DMA 1
! DMA 2
! Register name
|-
| 0x00
| 0xC0
| Address Register channel 0/4
|-
| 0x01
| 0xC1
| Count Register channel 0/4
|-
| 0x02
| 0xC2
| Address Register channel 1/5
|-
| 0x03
| 0xC3
| Count Register channel 1/5
|-
| 0x04
| 0xC4
| Address Register channel 2/6
|-
| 0x05
| 0xC5
| Count Register channel 2/6
|-
| 0x06
| 0xC6
| Address Register channel 3/7
|-
| 0x07
| 0xC7
| Count Register channel 3/7
|}
; PageCommand Registers 0x08 and 0xD0 (Write)
<div>
<div style="float: left; margin: 5px">
{| {{wikitable}}
| 0x87
| channel 0
|-
|Bit 0x837
|Bit 6
| channel 1
|Bit 5
|Bit 4
|Bit 3
|Bit 2
|Bit 1
|Bit 0
|-
|DACKP
| 0x81
|DRQP
| channel 2
|EXTW
|-
|PRIO
| 0x82
|COMP
| channel 3
|COND
|ADHE
|MMT
|}
</div>
This register really shows how incompatible the 8237 is with the PC hardware.
<div style="float: left; margin: 5px">
* Let's start with EXTW and COMP. These increase the speed of DMA transfer by 25% be removing one of the clock cycles. Does it work? No.
{| {{wikitable}}
* PRIO. When zeroed, this allows DMA priorities to be rotated allowing freedom and liberty for all peripherals that share the data bus. Does it work? No.
| 0x8F
* MMT and ADHE. Did you know that the IBM PC could do memory to memory transfers since 1981? That's right, hardware sprites, hardware frame buffering from one location to another. Does it work? No.
| channel 4 (useless due to cascading)
* COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This is one way to set up multiple DMA channels without masking each and every channel.
|-
| 0x8B
| channel 5
|-
| 0x89
| channel 6
|-
| 0x8A
| channel 8
|}
</div>
<div style="clear:both"> </div>
</div>
;Request Registers 0x09 and 0xD2 (Write)
For the pedantic among you, the page and address registers are actually used (not in modern PCs). These registers hold the next DRAM memory address to be refreshed. The reason it is useless today is because the registers can only address 16 MB of memory with these registers, and the CPU needs to be involved to 'up' the page register per 64 KB, which it can't because the DMA controller has no ability to inform the CPU it needs to be updated, because IBM forgot to connect the pins of the DMA controller to interrupts because they cost-cut on building the original PC motherboard! (Please don't feed that sentence through a grammar checker.)
Used for memory to memory transfers and setting up priority rotation -- absolutely useless.
;"Intermediate" Registers 0x0D and 0xDA (Read)
'''Note:''' That the number of bytes transferred is one more than the count programmed for the channel. So programming count = 0 will transfer one byte, while programming count = 0xffff will transfer the full 64k.
Never implemented on PCs. Useless.
== Examples ==
== [[Floppy Driver|Floppy Disk]] DMA Programming ==
=== Floppy Disk DMA Initialization ===
After all that ranting, the next section may come as something of a let down. Firstly - you need implement only 3 routines to perform a DMA transfer. The example I am using is the Floppy Drive controller (probably the most common followed Sound Blaster).
You need only implement 1 to 3 tiny routines to perform a DMA transfer. This example is the Floppy Drive controller (probably the most common followed by SoundBlaster).
So putting it all together - let's set up a DMA buffer for channel 2 (the floppy disk).
Note: the following code is not optimal, because there is an OUT to the same IO port twice (in two places). This causes an extra delay on the IO Port
<pre>
bus. Real code should separate the two "out 0x4" and "out 0x5" calls with an "out" to some other port.
<syntaxhighlight lang="asm">
initialize_floppy_DMA:
; set DMA channel 2 to transfer data from 00x1000 - 64k0x33ff in memory
; paging must map this _physical_ memory elsewhere and _pin_ it from paging to disk!
; set the counter to 0x23ff, the length of a track on a 1.44 MiB floppy - 1 (assuming 512 byte sectors)
; transfer length = counter + 1
; the length of transfer is programmed count+1 (check the data sheet if you want)
out 0x0a, 0x06 ; mask DMA channel 2 and 0 (assuming 0 is already masked)
out 0xd80x0c, 0xFF ; reset the master flip-flop
out 0x04, 0 ; address to 0 (low byte)
out 0x04, 0 0x10 ; address to 00x10 (high byte)
out 0xd80x0c, 0xFF ; reset the master flip-flop (again!!!)
out 0x05, 0xFF ; count to 0x23ff (low byte)
out 0x05, 0x23 ; count to 0x23ff (high byte),
out 0x81, 0 ; external page register to 0 for total address of 00 0010 00
out 0x0a, 0x02 ; unmask DMA channel 2
ret
</syntaxhighlight>
</pre>
Please note: if you wanted to be stingy about memory, you can use any of the memory above the amount of the maximum transfer allowed (0x2400 in this case). Once you have set up your addressingstart address and amount of transfer length you do not need to touch it again, toif selectyou readingare orusing writingautoinit. youOnce usereading theor mode register.writing
is selected, you don't need to change that, either. To ''change'' selecting reading or writing you use the mode register.
<syntaxhighlight lang="asm">
<pre>
prepare_for_floppy_DMA_write:
out 0x0a, 0x06 ; mask DMA channel 2 and 0 (assuming 0 is already masked)
out 0x0b, 0x5A ; 01011010
; single transfer, address increment, autoinit, write, channel2)
prepare_for_floppy_DMA_read:
out 0x0a, 0x06 ; mask DMA channel 2 and 0 (assuming 0 is already masked)
out 0x0b, 0x56 ; 01010110
; single transfer, address increment, autoinit, read, channel2)
out 0x0a, 0x02 ; unmask DMA channel 2
ret
</syntaxhighlight>
</pre>
Some hardware, as well as VirtualPC do not support autoinit. You may want to set the Mode registers to 0x4A and 0x46 in the above routines, instead.
'''Comment: Due to problems with autoinit on real hardware and MS Virtual PC, you might better avoid autoinit and use this code:'''
The above routines use single transfer mode for compatibility, but during the initialization of your floppy driver if you detect an "advanced" floppy
<pre>
controller (using the Version command), "demand transfer" should be used to reduce overhead.
prepare_for_floppy_DMA_write:
out 0x0a, 0x06 ; mask DMA channel 2
out 0x0b, 0x4A ; 01001010
; single transfer, address increment, write, channel2)
out 0x0a, 0x02 ; unmask DMA channel 2
ret
== References ==
prepare_for_floppy_DMA_read:
out 0x0a, 0x06 ; mask DMA channel 2
out 0x0b, 0x46 ; 01000110
; single transfer, address increment, read, channel2)
out 0x0a, 0x02 ; unmask DMA channel 2
ret
</pre>
=== Articles ===
Use initialize_floppy_DMA just before prepare_for_floppy_DMA_read/write and the actual floppy_disk_read/write process.
* [[Floppy Disk Controller]]
* [[Sound Blaster 16]]
The above uses single transfer only for compatibility, but during the initialization of your floppy driver if you detect a different floppy controller (using the init command), demand transfer should be used to reduce overhead. In this case for a read the:
out 0x0b, 0x56
would change to:
out 0x0b, 0x16.
=== Usage ===
;Initialization
During the initialization of your floppy driver:
* Map enough physical memory to virtual memory for the size of transfer you are going to do.
* ''(No more than 64k, all transfers to be sone in 64k chunks.)''
* ''(Memory must begin on a 64k boundary from between 0 and 16 MiB.)''
* Pin the pages allocated so you don't get page faults during reads or writes.
* Call initialize_floppy_DMA altered with suitable values.
;For a write
* Call prepare_for_floppy_DMA_write.
* Copy 18 sectors worth of information to your DMA buffer.
* Send a write command to the floppy controller for 18 sectors (say track 1).
* The floppy will now write 18 sectors of information!
* Copy 18 sectors worth of information to your DMA buffer.
* Send a write command to the floppy controller for 18 sectors (say track 2).
Note that there is no need to fiddle with the DMA addressing - it automatically resets itself to 0x0 ready for another transaction.
;For a read
* Call prepare_for_floppy_DMA_read.
* Send a read command to the floppy controller for 18 sectors (say track 1).
* Multiply the sector you wanted by 512 and use that as an offset into the DMA buffer..
* On the next read you can see if the track you want is in the buffer already and go straight to it. (This is called track buffering.)
The good thing about this setup is that it is simple and fast. There is no need to set up a track caching scheme and associated code (apart from checking if the current track number is in the cache).
I wouldn't advise trying to improve the speed of floppy access any further, the floppy disk is so slow compared to the rest of the computer another 1 millisecond of your time is going to be unnoticeable. Perhaps the only real improvement that could be made is to read in track 0 on the first read of a floppy disk and buffer the FAT (File Allocation Table) or Inode information. This would only be useful if you were never going to write to the floppy, as the first append to a file will force the OS to update the FAT in memory, copy the altered track 0 to the DMA buffer and perform a floppy write.
Putting it simply, there's no real way to improve the write-performance of a floppy disk unless you are writing entire tracks of information at once and aiming for the fastest floppy formatting time record!
== In Conclusion ==
As I've (constantly) pointed out the DMA chip has lot's of useful features. The main point in programming the chip is remembering the features that '''don't''' work. Regardless of the problems, the less the DMA chip is used the better because of it's negative impact on system performance (4.77 MHz, 8-bit data transfer). USB floppy disk drives are now available and standard interface floppy disk drives are only an option on some systems. The future will only make this more so.
== References ==
=== Articles ===
* [[ATA/ATAPI using DMA]]
* [[ADMA]]
=== External Links ===
* [http://www.stud.fhintel-hannoverassembler.deit/~heinemanPORTALE/extern4/231466231466_8237A_DMA.pdf Intel 8237A datasheet]
*[http://bos.asmhackers.net/docs/dma/docs/ http://bos.asmhackers.net/docs/dma/docs/]
[[Category:Storage]]
[[de:DMA]]
| 