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ISA DMA: Difference between revisions
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* Transfers must be physically contiguous, and can only target the lowest 16 MB of physical memory;
* ISA DMA is slow - theoretically 4.77 MB/second, but more like 400 KB/second due to ISA bus protocols;
* ISA DMA frees up CPU resources, but
* Very few devices currently use ISA DMA -- only internal floppies, some embedded sound chips, some parallel ports, and some serial ports.
Notes:
* Sound Blaster and Sound Blaster PRO only support 8 bit DMA;
* [[Sound Blaster 16]]+ supports both;
* [[Floppy disk controllers]] only support 8 bit DMA and are hardwired to use DMA Channel 2.
== There Is More Than One Kind of DMA on a PC ==
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== ISA DMA Background ==
'''ISA DMA''' (''Industry Standard Architecture Direct Memory Access''), like ISA itself, is an [https://en.wikipedia.org/wiki/Appendix_(anatomy) appendix] for modern PCs. It is used by the
internal floppy disk controller, ISA sound cards, ISA network cards, and parallel ports (if they support ECP mode). Whilst interrupt, keyboard
and timer interface circuits have obvious and relevant uses, the ISA DMA controller and its programming interface are still well and truly stuck in the
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interrupt. This implies that all peripherals using an ISA DMA channel are limited to no more than 64 KB transfers for fear of upsetting the DMA controller.
Even with the PC/AT, IBM began bypassing the ISA DMA used in the PC/XT and used [[ATA PIO Mode]] for the hard disk. This
was because of the 64 KB limitations outlined above and the fact that the 286 processor could perform 16 bit transactions at 6 MHz. Even the ISA bus could
run at a speed of up to 12 MHz, far faster than the 4.77 MHz the DMA controller was running at.
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== Technical Details ==
Each 8237 DMA chip has 4 DMA channels. DMA0-DMA3 on the first chip and DMA4-DMA7 on the second. The first DMA controller is wired up for 8 bit transfers,
while the second is wired up for 16 bit transfers. On some tutorials or other wiki articles, you will sometimes see the '''second''' DMA chip (channels 4 to 7) labeled as the "'''master'''" controller, and the first (channels 0 to 3) called the "slave". This is highly confusing, and these terms will not be used again, here.
DMA Channel 0 is unavailable as it was used for a short time for DRAM memory refresh, and remains reserved because of this (even though modern computers
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This creates two serious problems. One is "contention issues". The other is that it is difficult to be sure what state the flip-flop is currently in.
The standard solution for dealing with the flip-flop state issue is to reset the flip-flop to "low byte" state every single time you want to use it, just
so you can be certain it is in the proper state before sending bytes. There are only two solutions to "contention": either use a [[lock]], or allow only
one ISA DMA driver, so that contention is impossible.
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The master and slave DMA controllers are very similar, so (to save space) both of them have been combined into the following table. Please try
not to let this confuse you.
Note: for Address and Count Registers on channels 5 to 7, see [[#16 bit issues|16 bit issues]] above.
Each 8237A has 18 registers, addressed via the I/O Port bus:
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|0xC0
|Word
|
|Start Address Register channel 0/4 (unusable)
|-
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* MMT and ADHE. Did you know that the IBM PC could do memory to memory transfers since 1981? That's right, hardware sprites, hardware frame buffering from one location to another. Does it work? No.
* COND. Hooray the only bit in the control register that does something useful. Setting this bit disables the DMA controller. This is one way to set up multiple DMA channels without masking each and every channel.
;Request Registers 0x09 and 0xD2 (Write)
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bus. Real code should separate the two "out 0x4" and "out 0x5" calls with an "out" to some other port.
<
initialize_floppy_DMA:
; set DMA channel 2 to transfer data from 0x1000 - 0x33ff in memory
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; set the counter to 0x23ff, the length of a track on a 1.44 MiB floppy - 1 (assuming 512 byte sectors)
; transfer length = counter + 1
out 0x0a,
out 0x0c, 0xFF ; reset the master flip-flop
out 0x04, 0 ; address to 0 (low byte)
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out 0x05, 0x23 ; count to 0x23ff (high byte),
out 0x81, 0 ; external page register to 0 for total address of 00 10 00
out 0x0a,
ret
</syntaxhighlight>
Once you have set up your start address and transfer length you do not need to touch it again, if you are using autoinit. Once reading or writing
is selected, you don't need to change that, either. To ''change'' selecting reading or writing you use the mode register.
<
prepare_for_floppy_DMA_write:
out 0x0a,
out 0x0b, 0x5A ; 01011010
; single transfer, address increment, autoinit, write, channel2)
out 0x0a,
ret
prepare_for_floppy_DMA_read:
out 0x0a,
out 0x0b, 0x56 ; 01010110
; single transfer, address increment, autoinit, read, channel2)
out 0x0a,
ret
</syntaxhighlight>
Some hardware, as well as VirtualPC do not support autoinit. You may want to set the Mode registers to 0x4A and 0x46 in the above routines, instead.▼
▲set the Mode registers to 0x4A and 0x46 in the above routines, instead.
The above routines use single transfer mode for compatibility, but during the initialization of your floppy driver if you detect an "advanced" floppy
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=== Articles ===
* [[Floppy Disk Controller]]
* [[Sound Blaster 16]]
=== External Links ===
* [http://www.intel-assembler.it/PORTALE/4/231466_8237A_DMA.pdf Intel 8237A datasheet]
*[http://bos.asmhackers.net/docs/dma/docs/ http://bos.asmhackers.net/docs/dma/docs/]
[[Category:Storage]]
[[de:DMA]]
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