ISA DMA: Difference between revisions

* Transfers must be physically contiguous, and can only target the lowest 16 MB of physical memory;

* ISA DMA is slow - theoretically 4.77 MB/second, but more like 400 KB/second due to ISA bus protocols;

* Very few devices currently use ISA DMA -- only internal floppies, some embedded sound chips, some parallel ports, and some serial ports.

 

Notes:

* Sound Blaster and Sound Blaster PRO only support 8 bit DMA;

 

== There Is More Than One Kind of DMA on a PC ==

 

== ISA DMA Background ==

internal floppy disk controller, ISA sound cards, ISA network cards, and parallel ports (if they support ECP mode). Whilst interrupt, keyboard

and timer interface circuits have obvious and relevant uses, the ISA DMA controller and its programming interface are still well and truly stuck in the

== Technical Details ==

Each 8237 DMA chip has 4 DMA channels. DMA0-DMA3 on the first chip and DMA4-DMA7 on the second. The first DMA controller is wired up for 8 bit transfers,

 

DMA Channel 0 is unavailable as it was used for a short time for DRAM memory refresh, and remains reserved because of this (even though modern computers

interrupt when a transfer completes. However, some peripherals may '''not''' send an interrupt if a transfer fails with an error. As always, timeouts

are important.

=== The Registers ===

The master and slave DMA controllers are very similar, so (to save space) both of them have been combined into the following table. Please try

not to let this confuse you.

Note: for Address and Count Registers on channels 5 to 7, see [[#16 bit issues|16 bit issues]] above.

 

 

;Single Channel Mask Registers 0x0A and 0xD4 (Write)

{| {{wikitable}}

|-

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Use the SEL 0 and 1 bits to select the channel, and the MASK_ON bit to set or clear masking for it.

Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.

|}

 

to know the desired mask states of ''all'' the channels at that moment. There are several ways to do this, but one is simply to read this register, first.

Note that masking DMA channel 4 will mask 7, 6, 5 and 4 due to cascading.

bus. Real code should separate the two "out 0x4" and "out 0x5" calls with an "out" to some other port.

 

initialize_floppy_DMA:

; set DMA channel 2 to transfer data from 0x1000 - 0x33ff in memory

; set the counter to 0x23ff, the length of a track on a 1.44 MiB floppy - 1 (assuming 512 byte sectors)

; transfer length = counter + 1

out 0x0c, 0xFF ; reset the master flip-flop

out 0x04, 0 ; address to 0 (low byte)

out 0x05, 0x23 ; count to 0x23ff (high byte),

out 0x81, 0 ; external page register to 0 for total address of 00 10 00

ret

 

Once you have set up your start address and transfer length you do not need to touch it again, if you are using autoinit. Once reading or writing

is selected, you don't need to change that, either. To ''change'' selecting reading or writing you use the mode register.

 

prepare_for_floppy_DMA_write:

out 0x0b, 0x5A ; 01011010

; single transfer, address increment, autoinit, write, channel2)

ret

 

prepare_for_floppy_DMA_read:

out 0x0b, 0x56 ; 01010110

; single transfer, address increment, autoinit, read, channel2)

ret

 

 

The above routines use single transfer mode for compatibility, but during the initialization of your floppy driver if you detect an "advanced" floppy

=== Articles ===

* [[Floppy Disk Controller]]

 

=== External Links ===

* [http://www.intel-assembler.it/PORTALE/4/231466_8237A_DMA.pdf Intel 8237A datasheet]

 

[[Category:Storage]]