IOAPIC: Difference between revisions

In order to detect the existence of an I/O APIC (or multiple ones), the Intel Multi-Processor or [[RSDP|ACPI]] tables (specifically, the [[MADT]]) must be parsed. In the MP tables, configuration tables with the entry identification of 0x02 are for I/O APICs. Parsing will tell how many (if any) I/O APICs exist, what are their APIC ID, base MMIO address and first IRQ (or GSI - Global System Interrupt). For more information ofon parsing the MP tables, see the External MP Tables Links section below. So you can have, say, 2 I/O APICs, the first handling IRQs 0 - 23 and the second 24 - 47.

Each I/O APIC has a set of 2 or 3 (depending on version) 32-bit registers and up to many 64-bit registers (one per IRQ). The 64-bit registers have actually to be accessed as two 32-bit reads/writes. All registers are memory indexed. It means that you actually have only two 32-bit registers in memory, called IOREGSEL and IOREGWIN. You put the register index in IOREGSEL, and then you can read/write in IOREGWIN. The first three registers contain general informationsinformation about this I/O APIC, while the remaingremaining registers contain the specific configuration for each of the IRQsIRQ.

This register has index 0 (you write 0 to IOREGSEL and then read from IOREGWIN). It's a Read -Only registersregister with almost all bits reserved. The only interesting field is in bits 24 - 27: the APIC ID for this device (each peripheral which is interfaced with the APIC Bus needs an APIC ID, not only CPUs). You shall find this ID in ACPI/MP Tables as well.

* [https://web.archive.org/web/20121002210153/http://download.intel.com/design/pentiumarchives/processors/pro/datashtsdocs/24201606.pdf Intel MultiProcessor Specification]

* [http://download.intel.com/design/chipsets/datashts/29056601.pdf Intel 82093AA I/O APIC] (dead link)

* [http://download.intel.com/design/processor/manuals/253668.pdf Intel SDM 3A (see ch. 9.9)] (dead link)