IOAPIC: Difference between revisions

2,918 bytes removed ,  6 years ago
m
Reverted edits by Shukantpal (talk) to last revision by Michaelpetch
[unchecked revision][unchecked revision]
(IOAPIC Signals Description)
m (Reverted edits by Shukantpal (talk) to last revision by Michaelpetch)
Line 77:
/* tell IOREGSEL where we want to read from */
*(volatile uint32_t*)(apic_base) = offset;
''Italic text'' /* return the data from IOWIN */
return *(volatile uint32_t*)(apic_base + 0x10);
}
</source>
'apic_base' is the memory base address for a selected IOAPIC, these can be found by enumerating them from the MP or ACPI Tables.
 
== Interrupt Signals ==
 
{| class="wikitable"
|-
! Signal Name
! Description
|-
| INTIN0
| '''Interrupt Input 0:''' This signal may be connected to the (INTR signal on) PIIX3 to communicate the status of IRQ0 and IRQ13 signals. It is important to note that IRQ0 and IRQ13 ''are embedded in PIIX3 and are not available to rest of the system.'' This input is connected to the redirection-table entry 0.
|-
| INTIN1
| '''Interrupt Input 1:''' This signal should be connected to the keyboard input (IRQ1). It is connected to the redirection-table entry 1.
|-
| INTIN2
| '''Interrupt Input 2:''' According to the IOAPIC datasheet, if IRQ0 is available to hardware, then it will be connected to this pin. That means that IRQ0 (could be) mapped to this input, which is connected to redirection-table entry 2.
|-
| INTIN[3:11,14,15]
| '''Interrupt Inputs 3 to 11, 14 and 15:''' This signals are connected to the ISA interrupts IRQ 3 to 11, 14 and 15. It may be useful to note that IRQ 8 is for interrupts that are asserted/active at low voltage level. These input signals are connected to their respective redirection-table entries.
|-
| INTIN12
| '''Interrupt Input 12:''' This signal should be connected to mouse input. It is connected to redirection-entry 12.
|-
| INTIN13
| '''Interrupt Input 13:''' If IRQ13 is available in hardware, then it will be connected to this signal. But if it isn't then IRQ13 is routed through PIIX3's INTR signal and it becomes INTIN13. I don't think that this is important from the software perspective. It is connected to redirection-entry 13.
|-
| INTIN[16:19]
| These signals are connected to PCI interrupts PIRQ[0:3]. The steering of PCI interrupts to ISA interrupts is performed by the IOAPIC using the software-defined redirection entries. These signals are connected to redirection-entries 16 to 19.
|-
| INTIN[20:21]
| These signals are usually connected to '''motherboard interrupts''' MIRQ[0:1]. They can be used for INIT or NMI signals or for general purpose interrupts. They are connected to redirection-table entries 20 and 21.
|-
| INTIN22
| This is a general purpose interrupt connected to redirection-table entry 22.
|-
| INTIN23/SMI
| This input has a special feature for SMI interrupt routing. Note that SMI interrupts are asserted at a low voltage level (if needed). If the mask bit is clear, then the interrupt will be sent like any other interrupt over the APIC bus to other APICs. But if the mask bit is set, then the interrupt will be routed through the SMIOUT output signal as an system-management interrupt. It is connected to redirection-table entry 23.
 
|-
| SMIOUT
| This is a special output signal which is in response to a SMI input on the 23rd IRQ in the IOAPIC. It is used when the mask bit in the 23rd re-direction table entry is set. But when the output bit isn't set, then the SMI input is sent over APIC bus. '''ToDo:''' Clear all this.
|}
 
== External Links ==
250

edits