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HPET: Difference between revisions
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:''This page is not meant as a full description of HPET, only as a lightweight introduction. If you need any information not covered by this article, consult the [http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf HPET specification].''
'''HPET''', or High Precision Event Timer, is a piece of hardware designed by Intel and Microsoft to replace older [[PIT]] and [[RTC]]. It consists of (usually 64-bit) main counter (which counts up), as well as from 3 to 32 32-bit or 64
▲HPET, or High Precision Event Timer, is a piece of hardware designed by Intel and Microsoft to replace older [[PIT]] and [[RTC]]. It consists of (usually 64-bit) main counter (which counts up), as well as from 3 to 32 32 or 64 bit wide comparators. HPET is programmed using memory mapped IO, and the base address of HPET can be found using [[ACPI]].
==Detecting HPET using ACPI==
The [http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf HPET specification] defines an ACPI 2.0 table that is to be used to detect presence, address and capabilities of HPET present in the system. If this table doesn't exist, you should assume there is no HPET and you should fall back to [[PIT]] or the [[APIC timer]].
<
struct address_structure
{
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uint8_t reserved:1;
uint8_t legacy_replacement:1;
address_structure address;
uint8_t hpet_number;
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uint8_t page_protection;
} __attribute__((packed));
</syntaxhighlight>
==HPET - timer vs comparators==
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!Type
|-
|0x000 -
|General Capabilities and ID Register
|Read only
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|63:32
|COUNTER_CLK_PERIOD
|Main counter tick period in
|-
|31-16
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General initialization:
1. Find HPET base address in 'HPET' ACPI table.
2. Calculate HPET frequency (f = 10^15 / period).
3. Save minimal tick (either from ACPI table or configuration register).
4. Initialize comparators.
5. Set ENABLE_CNF bit.
Timer N initialization:
1. Determine if timer N is periodic capable, save that information to avoid re-reading it every time.
2. Determine allowed interrupt routing for current timer and allocate an interrupt for it.
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To enable one-shot mode:
<
// "time" is time in
if (time < COUNTER_CLK_PERIOD)
{
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write_register_64(timer_configuration(n), (ioapic_input << 9) | (1 << 2));
write_register_64(timer_comparator(n), read_register(main_counter) + time);
</syntaxhighlight>
I hope the above code is obvious. If it's not, please analyze the meaning of specific fields in registers used above.
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To enable periodic mode:
<
// "time" is time in
if (time < COUNTER_CLK_PERIOD)
{
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write_register_64(timer_comparator(n), read_register(main_counter) + time);
write_register_64(timer_comparator(n), time);
</syntaxhighlight>
This snippet requires some more comments.
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==See also==
* [[IOAPIC]]
* [[APIC]]
* [[APIC timer]]
* [[PIT]]
* [[RTC]]
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[[Category:Common Devices]]
[[Category:Interrupts]]
[[Category:
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