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fixed reference to TSS Descriptor in Intel SDM
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The '''Global Descriptor Table''' ('''GDT''') is a binary data structure specific to the [[IA32_Architecture_Family
It is recommended to read the [[GDT Tutorial]].
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The '''GDT''' is pointed to by the value in the '''GDTR''' register. This is loaded using the '''LGDT''' assembly instruction, whose argument is a pointer to a '''GDT Descriptor''' structure:
{| class="wikitable"
|+ GDT Descriptor (GDTR)
!style="width: 66%; text-align: left;" |79 (64-bit mode) <br> 48 (32-bit mode) <span style="float: right;">16</span>
!style="width: 34%; text-align: left; vertical-align: bottom;" |15 <span style="float: right;">0</span>
|-
|'''Offset'''<br>63 (64-bit mode) <br> 31 (32-bit mode) <span style="float: right;">0</span>
|'''Size'''<br><br>15 <span style="float: right;">0</span>
|}
* '''Size:''' The size of the table in bytes subtracted by 1. This subtraction occurs because the maximum value of '''Size''' is 65535, while the '''GDT''' can be up to 65536 bytes in length (8192 entries). Further, no '''GDT''' can have a size of 0 bytes.
* '''Offset:''' The linear address of the '''GDT''' (not the physical address, paging applies).
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The entries in the '''GDT''' are 8 bytes long and form a table like this:
{|class="wikitable"
|+ Global Descriptor Table
! Address !! Content
|-
| GDTR Offset + 0 || Null
|-
| GDTR Offset + 8 || Entry 1
|-
| GDTR Offset + 16 || Entry 2
|-
| GDTR Offset + 24 || Entry 3
|- style="text-align: center;"
| '''...''' || '''...'''
|}
The first entry in the '''GDT''' (Entry 0) should always be null and subsequent entries should be used instead.
Entries in the table are accessed by '''[[Segment Selector|Segment Selectors]]''', which are loaded into '''[[Segmentation]]''' registers either by assembly instructions or by hardware functions such as '''[[Interrupts]]'''.
== Segment Descriptor ==
Each entry in the table
{| class="wikitable"
|+ Segment Descriptor
!style="width: 20%; text-align: left;"|63 <span style="float: right;">56</span>
!style="width: 12.5%; text-align: left;"|55 <span style="float: right;">52</span>
!style="width: 12.5%; text-align: left;"|51 <span style="float: right;">48</span>
!style="width: 25%; text-align: left;"|47 <span style="float: right;">40</span>
!style="width: 25%; text-align: left;"|39 <span style="float: right;">32</span>
|-
|'''Base'''<br>31 <span style="float: right;">24</span>
|'''Flags'''<br>3 <span style="float: right;">0</span>
|'''Limit'''<br>19 <span style="float: right;">16</span>
|'''Access Byte'''<br>7 <span style="float: right;">0</span>
|'''Base'''<br>23 <span style="float: right;">16</span>
|-
!colspan=3 style="text-align: left;"|31 <span style="float: right;">16</span>
!colspan=2 style="text-align: left;"|15 <span style="float: right;">0</span>
|-
|colspan=3|'''Base'''<br>15 <span style="float: right;">0</span>
|colspan=2|'''Limit'''<br>15 <span style="float: right;">0</span>
|}
* '''Base:''' A 32-bit value containing the linear address where the segment begins.
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For more information, see '''Section 3.4.5: Segment Descriptors''' and '''Figure 3-8: Segment Descriptor''' of the Intel Software Developer Manual, Volume 3-A.
{| class="wikitable"
|+ Access Byte
|-
!style="width: 12.5%;"|7
!style="width: 12.5%;"|6
!style="width: 12.5%;"|5
!style="width: 12.5%;"|4
!style="width: 12.5%;"|3
!style="width: 12.5%;"|2
!style="width: 12.5%;"|1
!style="width: 12.5%;"|0
|-
|'''P''' ||colspan=2|'''DPL''' || '''S''' || '''E''' || '''DC''' || '''RW''' || '''A'''
|}
* '''P:''' Present bit. Allows an entry to refer to a valid segment. Must be set ('''1''') for any valid segment.
* '''DPL:''' Descriptor privilege level field. Contains the [[Security#Rings|CPU Privilege level]] of the segment. '''0''' = highest privilege (kernel), '''3''' = lowest privilege (user applications).
* '''S:''' Descriptor type bit. If clear ('''0''') the descriptor defines a system segment (eg. a [[Task_State_Segment|Task State Segment]]). If set ('''1''') it defines a code or data segment.
* '''
* '''DC:''' Direction bit/Conforming bit.
** For data selectors: Direction bit. If clear ('''0''') the segment grows up. If set ('''1''') the segment [[Expand_Down|grows down]], ie. the '''Offset''' has to be greater than the '''Limit'''.
** For code selectors: Conforming bit.
*** If clear ('''0''') code in this segment can only be executed from the ring set in '''
*** If set ('''1''') code in this segment can be executed from an equal or lower privilege level. For example, code in ring 3 can far-jump to ''conforming'' code in a ring 2 segment. The '''
* '''RW:''' Readable bit/Writable bit.
** For code segments: Readable bit. If clear ('''0'''), read access for this segment is not allowed. If set ('''1''') read access is allowed. Write access is never allowed for code segments.
** For data segments: Writeable bit. If clear ('''0'''), write access for this segment is not allowed. If set ('''1''') write access is allowed. Read access is always allowed for data segments.
* '''A:''' Accessed bit. The CPU will set it when the segment is accessed unless set to '''1''' in advance. This means that in case the GDT descriptor is stored in read only pages and this bit is set to '''0''', the CPU trying to set this bit will trigger a page fault. Best left set to '''1''' unless otherwise needed.
{| class="wikitable"
|+ Flags
|-
!style="width: 25%;"|3
!style="width: 25%;"|2
!style="width: 25%;"|1
!style="width: 25%;"|0
|-
|'''G''' || '''DB''' || '''L'''
|Reserved
|}
* '''G:''' Granularity flag, indicates the size the '''Limit''' value is scaled by. If clear ('''0'''), the '''Limit''' is in 1 Byte blocks (byte granularity). If set ('''1'''), the '''Limit''' is in 4 KiB blocks (page granularity).
* '''DB:''' Size flag. If clear ('''0'''), the descriptor defines a 16-bit protected mode segment. If set ('''1''') it defines a 32-bit protected mode segment. A GDT can have both 16-bit and 32-bit selectors at once.
* '''L:''' Long-mode code flag. If set ('''1'''), the descriptor defines a 64-bit code segment. When set, '''DB''' should always be clear. For any other type of segment (other code types or any data segment), it should be clear ('''0''').
== System Segment Descriptor ==
For system segments, such as those defining a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''', the format of the '''Access Byte''' differs slightly, in order to define different types of system segments rather than code and data segments.
For more information, see '''Section 3.5: System Descriptor Types''' and '''Figure 3-2: System-Segment and Gate-Descriptor Types''' of the Intel Software Developer Manual, Volume 3-A.
{| class="wikitable"
|+ Access Byte
|-
!style="width: 12.5%;"|7
!style="width: 12.5%;"|6
!style="width: 12.5%;"|5
!style="width: 12.5%;"|4
!style="width: 12.5%;"|3
!style="width: 12.5%;"|2
!style="width: 12.5%;"|1
!style="width: 12.5%;"|0
|-
|'''P''' ||colspan=2|'''DPL''' || '''S''' || colspan=4|'''Type'''
|}
* '''Type:''' Type of system segment.
Types available in 32-bit protected mode:
* '''0x1:''' 16-bit TSS (Available)
* '''0x2:''' LDT
* '''0x3:''' 16-bit TSS (Busy)
* '''0x9:''' 32-bit TSS (Available)
* '''0xB:''' 32-bit TSS (Busy)
Types available in Long Mode:
* '''0x2:''' LDT
* '''0x9:''' 64-bit TSS (Available)
* '''0xB:''' 64-bit TSS (Busy)
== Long Mode System Segment Descriptor ==
For a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''' in '''[[Long Mode]]''', the format of a '''Segment Descriptor''' differs to ensure that the '''Base''' value can contain a 64-bit '''[[Linear Address]]'''. It takes up the space in the table of two usual entries, in a little endian format, such that the lower half of this entry precedes the higher half in the table.
For more information, see '''Section 8.2.3: TSS Descriptor in 64-bit Mode''' and '''Figure 8-4: Format of TSS and LDT Descriptors in 64-bit Mode''' of the Intel Software Developer Manual, Volume 3-A.
{| class="wikitable" style="display: inline-table;"
|+ 64-bit System Segment Descriptor
|-
!colspan=5 style="text-align: left;"|127 <span style="float: right;">96</span>
|-
|colspan=5|Reserved
|-
!colspan=5 style="text-align: left;"|95 <span style="float: right;">64</span>
|-
|colspan=5|'''Base'''<br>63 <span style="float: right;">32</span>
|-
!style="width: 20%; text-align: left;"|63 <span style="float: right;">56</span>
!style="width: 12.5%; text-align: left;"|55 <span style="float: right;">52</span>
!style="width: 12.5%; text-align: left;"|51 <span style="float: right;">48</span>
!style="width: 25%; text-align: left;"|47 <span style="float: right;">40</span>
!style="width: 25%; text-align: left;"|39 <span style="float: right;">32</span>
|-
|'''Base'''<br>31 <span style="float: right;">24</span>
|'''Flags'''<br>3 <span style="float: right;">0</span>
|'''Limit'''<br>19 <span style="float: right;">16</span>
|'''Access Byte'''<br>7 <span style="float: right;">0</span>
|'''Base'''<br>23 <span style="float: right;">16</span>
|-
!colspan=3 style="text-align: left;"|31 <span style="float: right;">16</span>
!colspan=2 style="text-align: left;"|15 <span style="float: right;">0</span>
|-
|colspan=3|'''Base'''<br>15 <span style="float: right;">0</span>
|colspan=2|'''Limit'''<br>15 <span style="float: right;">0</span>
|}
== See Also ==
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* [http://files.osdev.org/mirrors/geezer/os/pm.htm Protected Mode tutorial]
* [http://www.intel.com/design/processor/manuals/253668.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:. System Programming Guide, Part 1 (order number 253668)] chapter 2.4
[[Category:X86 CPU]]
[[Category:Memory Segmentation]]
[[de:Global Descriptor Table]]
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