Global Descriptor Table: Difference between revisions

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fixed reference to TSS Descriptor in Intel SDM

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Revision as of 21:32, 20 April 2022 (view source) osdev>Mooofdoom m (Make flag names consistent in the explanations) ← Older edit		Latest revision as of 13:23, 27 January 2024 (view source) osdev>Cargo9511 m (fixed reference to TSS Descriptor in Intel SDM)
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Line 103: For code segments: Readable bit. If clear ('''0'''), read access for this segment is not allowed. If set ('''1''') read access is allowed. Write access is never allowed for code segments. For data segments: Writeable bit. If clear ('''0'''), write access for this segment is not allowed. If set ('''1''') write access is allowed. Read access is always allowed for data segments. * '''A:''' Accessed bit. The CPU will set it when the segment is accessed unless set to '''1''' in advance. This means that in case the GDT descriptor is stored in read only pages and this bit is set to '''0''', the CPU trying to set this bit will trigger a page fault. Best left set to '''1''' unless otherwise needed. * '''A:''' Accessed bit. Best left clear ('''0'''), the CPU will set it when the segment is accessed. {\| class="wikitable" Line 149: * '''0x3:''' 16-bit TSS (Busy) * '''0x9:''' 32-bit TSS (Available) * '''0xB:''' 32-bit TSS (~~Available~~Busy) Types available in Long Mode: * '''0x2:''' LDT * '''0x9:''' 64-bit TSS (Available) * '''0xB:''' 64-bit TSS (~~Available~~Busy) == Long Mode System Segment Descriptor == Line 160: For a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''' in '''[[Long Mode]]''', the format of a '''Segment Descriptor''' differs to ensure that the '''Base''' value can contain a 64-bit '''[[Linear Address]]'''. It takes up the space in the table of two usual entries, in a little endian format, such that the lower half of this entry precedes the higher half in the table. For more information, see '''Section 78.2.3: TSS Descriptor in 64-bit Mode''' and '''Figure 78-4: Format of TSS and LDT Descriptors in 64-bit Mode''' of the Intel Software Developer Manual, Volume 3-A. {\| class="wikitable" style="display: inline-table;" Line 202: * [http://files.osdev.org/mirrors/geezer/os/pm.htm Protected Mode tutorial] * [http://www.intel.com/design/processor/manuals/253668.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:. System Programming Guide, Part 1 (order number 253668)] chapter 2.4~~[[Category:X86 CPU]]~~ [[Category:X86 CPU]] [[Category:Memory Segmentation]] [[de:Global Descriptor Table]]