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fixed reference to TSS Descriptor in Intel SDM

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Line 88: !style="width: 12.5%;"\|0 \|- \|'''PrP''' \|\|colspan=2\|'''~~Privl~~DPL''' \|\| '''S''' \|\| '''ExE''' \|\| '''DC''' \|\| '''RW''' \|\| '''AcA''' \|} * '''PrP:''' Present bit. Allows an entry to refer to a valid segment. Must be set ('''1''') for any valid segment. * '''~~Privl~~DPL:''' Descriptor privilege level field. Contains the [[Security#Rings\|CPU Privilege level]] of the segment. '''0''' = highest privilege (kernel), '''3''' = lowest privilege (user applications). * '''S:''' Descriptor type bit. If clear ('''0''') the descriptor defines a system segment (eg. a [[Task_State_Segment\|Task State Segment]]). If set ('''1''') it defines a code or data segment. * '''ExE:''' Executable bit. If clear ('''0''') the descriptor defines a data segment. If set ('''1''') it defines a code segment which can be executed from. * '''DC:''' Direction bit/Conforming bit. For data selectors: Direction bit. If clear ('''0''') the segment grows up. If set ('''1''') the segment [[Expand_Down\|grows down]], ie. the '''Offset''' has to be greater than the '''Limit'''. For code selectors: Conforming bit. * If clear ('''0''') code in this segment can only be executed from the ring set in '''~~Privl~~DPL'''. * If set ('''1''') code in this segment can be executed from an equal or lower privilege level. For example, code in ring 3 can far-jump to ''conforming'' code in a ring 2 segment. The '''~~Privl~~DPL''' field represent the highest privilege level that is allowed to execute the segment. For example, code in ring 0 cannot far-jump to a conforming code segment where '''~~Privl~~DPL''' is 2, while code in ring 2 and 3 can. Note that the privilege level remains the same, ie. a far-jump from ring 3 to a segment with a '''~~Privl~~DPL''' of 2 remains in ring 3 after the jump. * '''RW:''' Readable bit/Writable bit. For code segments: Readable bit. If clear ('''0'''), read access for this segment is not allowed. If set ('''1''') read access is allowed. Write access is never allowed for code segments. For data segments: Writeable bit. If clear ('''0'''), write access for this segment is not allowed. If set ('''1''') write access is allowed. Read access is always allowed for data segments. * '''A:''' Accessed bit. The CPU will set it when the segment is accessed unless set to '''1''' in advance. This means that in case the GDT descriptor is stored in read only pages and this bit is set to '''0''', the CPU trying to set this bit will trigger a page fault. Best left set to '''1''' unless otherwise needed. * '''Ac:''' Accessed bit. Best left clear ('''0'''), the CPU will set it when the segment is accessed. {\| class="wikitable" Line 113: !style="width: 25%;"\|0 \|- \|'''GrG''' \|\| '''SzDB''' \|\| '''L''' \|Reserved \|} * '''GrG:''' Granularity flag, indicates the size the '''Limit''' value is scaled by. If clear ('''0'''), the '''Limit''' is in 1 Byte blocks (byte granularity). If set ('''1'''), the '''Limit''' is in 4 KiB blocks (page granularity). * '''SzDB:''' Size flag. If clear ('''0'''), the descriptor defines a 16-bit protected mode segment. If set ('''1''') it defines a 32-bit protected mode segment. A GDT can have both 16-bit and 32-bit selectors at once. * '''L:''' Long-mode code flag. If set ('''1'''), the descriptor defines a 64-bit code segment. When set, '''SzDB''' should always be clear. For any other type of segment (other code types or any data segment), it should be clear ('''0'''). == System Segment Descriptor == For system segments, such as those defining a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''', the format of the '''Access Byte''' differs slightly, in order to define different types of system segments rather than code and data segments. For more information, see '''Section 3.5: System Descriptor Types''' and '''Figure 3-2: System-Segment and Gate-Descriptor Types''' of the Intel Software Developer Manual, Volume 3-A. {\| class="wikitable" \|+ Access Byte \|- !style="width: 12.5%;"\|7 !style="width: 12.5%;"\|6 !style="width: 12.5%;"\|5 !style="width: 12.5%;"\|4 !style="width: 12.5%;"\|3 !style="width: 12.5%;"\|2 !style="width: 12.5%;"\|1 !style="width: 12.5%;"\|0 \|- \|'''P'''    \|\|colspan=2\|'''DPL''' \|\| '''S''' \|\| colspan=4\|'''Type''' \|} * '''Type:''' Type of system segment. Types available in 32-bit protected mode: * '''0x1:''' 16-bit TSS (Available) * '''0x2:''' LDT * '''0x3:''' 16-bit TSS (Busy) * '''0x9:''' 32-bit TSS (Available) * '''0xB:''' 32-bit TSS (Busy) Types available in Long Mode: * '''0x2:''' LDT * '''0x9:''' 64-bit TSS (Available) * '''0xB:''' 64-bit TSS (Busy) == Long Mode System Segment Descriptor == For a '''[[Task State Segment]]''' or '''[[Local Descriptor Table]]''' in '''[[Long Mode]]''', the format of a '''Segment Descriptor''' differs to ensure that the '''Base''' value can contain a 64-bit '''[[Linear Address]]'''. It takes up the space in the table of two usual entries, in a little endian format, such that the lower half of this entry precedes the higher half in the table. For more information, see '''Section 8.2.3: TSS Descriptor in 64-bit Mode''' and '''Figure 8-4: Format of TSS and LDT Descriptors in 64-bit Mode''' of the Intel Software Developer Manual, Volume 3-A. {\| class="wikitable" style="display: inline-table;" \|+ 64-bit System Segment Descriptor \|- !colspan=5 style="text-align: left;"\|127   <span style="float: right;">96</span> \|- \|colspan=5\|Reserved \|- !colspan=5 style="text-align: left;"\|95   <span style="float: right;">64</span> \|- \|colspan=5\|'''Base'''<br>63   <span style="float: right;">32</span> \|- !style="width: 20%; text-align: left;"\|63   <span style="float: right;">56</span> !style="width: 12.5%; text-align: left;"\|55   <span style="float: right;">52</span> !style="width: 12.5%; text-align: left;"\|51   <span style="float: right;">48</span> !style="width: 25%; text-align: left;"\|47   <span style="float: right;">40</span> !style="width: 25%; text-align: left;"\|39   <span style="float: right;">32</span> \|- \|'''Base'''<br>31   <span style="float: right;">24</span> \|'''Flags'''<br>3   <span style="float: right;">0</span> \|'''Limit'''<br>19   <span style="float: right;">16</span> \|'''Access Byte'''<br>7   <span style="float: right;">0</span> \|'''Base'''<br>23   <span style="float: right;">16</span> \|- !colspan=3 style="text-align: left;"\|31   <span style="float: right;">16</span> !colspan=2 style="text-align: left;"\|15   <span style="float: right;">0</span> \|- \|colspan=3\|'''Base'''<br>15   <span style="float: right;">0</span> \|colspan=2\|'''Limit'''<br>15   <span style="float: right;">0</span> \|} == See Also == Line 131 ⟶ 202: * [http://files.osdev.org/mirrors/geezer/os/pm.htm Protected Mode tutorial] * [http://www.intel.com/design/processor/manuals/253668.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:. System Programming Guide, Part 1 (order number 253668)] chapter 2.4~~[[Category:X86 CPU]]~~ [[Category:X86 CPU]] [[Category:Memory Segmentation]] [[de:Global Descriptor Table]]