Generic Interrupt Controller versions 3 and 4: Difference between revisions

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Revision as of 02:27, 25 February 2019 (view source) osdev>Gravaera m (→‎Special IntIDs (and changes from GICv2)) ← Older edit		Latest revision as of 17:27, 9 July 2023 (view source) osdev>Khaledhammouda No edit summary
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Line 47: To enable affinity-based routing in the Distributor for Secure IRQs, set GICD_CTLR.ARE_S to 1. To enable affinity-based routing in the Distributor for non-secure IRQs, set GICD_CTLR.ARE_NS to 1. Changing the value of either or both of these bits from 1 to 0 is <UNPREDICTABLE>. Changing the value from 0 to 1 is <UNPREDICTABLE> unless both groups of interrupts (group0 and group1) are disabled. Specifically: * If GICD_CTLR.DS == 0, changing the value from 0 to 1 is <UNPREDICTABLE> when: GICD_CTLR.EnableGrp0 == 01. GICD_CTLR.EnableGrp1S == 01. ** GICD_CTLR.EnableGrp1NS == 01. * If GICD_CTLR.DS == 1, then changing the value from 0 to 1 is <UNPREDICTABLE> when: GICD_CTLR.EnableGrp0 == 01. GICD_CTLR.EnableGrp1 == 01. Software (the kernel) should ensure that the Distributor has commited the effects of these writes before proceeding, by polling GICD_CTLR.RWP before continuing. Line 70: == Participating nodes == Participating nodes are those PEs which are setup to be ready to receive an interrupt which is being delivered in 1 of N mode. In order to prepare a PE to take a 1 of N routed interrupt, that PE must be configured as follows: ~~See section 3.3.2, which I could not understand.~~ * GICR_WAKER.ProcessorSleep == 0, and the interrupt group of the interrupt must be enabled on that PE. * GICD_CTLR.E1NWF == 1. * GICR_TYPER.DPGS == 1. (DPGS = Disable Processor Group Selections). Furthermore, GICR_CTLR.{DPG1S, DPG1NS, DPG0} == 0. = IntIDs = Line 83 ⟶ 87: * PEs (Processor Interfaces) must implement either 16 or 24 bits of IntID. However, a system might have a mixture of PEs that support both sizes! * The ''Distributor and Redistributors must all implement the same number'' of ID bits. The ID bits for the Distributor and Redistributor must not exceed the minimum IntID size implemented by any single PE in the system. I.e, the Distributor and Redistributor IntID bit-width cannot must be smaller than or equal to the bit width of the smallest PE bit-width. * IFIf LPIs are ''not'' supported, the Distributor and Redistributors must implement at least 5 bits of IntID, and at most 10 bits of IntID. * If LPIs are supported, the Distributor and Redistributors must support at least 14 bits of IntID. * If an ITS exists, the ITS may implement any bit-width up to or equal to the bit-width of the Redistributors; and this bit width must be a minimum of 14 bits. Line 170 ⟶ 175: * [[http://www.wiki.xilinx.com/GIC\|Xilinx GIC Wiki page]] * [[http://ssup2.iptime.org/wiki/ARM_Generic_Interrupt_Controller_(GIC)\| Another Wiki page]] [[Category:ARM]] [[Category:Interrupts]]