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Generic Interrupt Controller versions 3 and 4: Difference between revisions

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To enable affinity-based routing in the Distributor for Secure IRQs, set GICD_CTLR.ARE_S to 1. To enable affinity-based routing in the Distributor for non-secure IRQs, set GICD_CTLR.ARE_NS to 1. Changing the value of either or both of these bits from 1 to 0 is <UNPREDICTABLE>. Changing the value from 0 to 1 is <UNPREDICTABLE> unless both groups of interrupts (group0 and group1) are disabled. Specifically:
* If GICD_CTLR.DS == 0, changing the value from 0 to 1 is <UNPREDICTABLE> when:
** GICD_CTLR.EnableGrp0 == 01.
** GICD_CTLR.EnableGrp1S == 01.
** GICD_CTLR.EnableGrp1NS == 01.
 
* If GICD_CTLR.DS == 1, then changing the value from 0 to 1 is <UNPREDICTABLE> when:
** GICD_CTLR.EnableGrp0 == 01.
** GICD_CTLR.EnableGrp1 == 01.
 
Software (the kernel) should ensure that the Distributor has commited the effects of these writes before proceeding, by polling GICD_CTLR.RWP before continuing.
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== Participating nodes ==
Participating nodes are those PEs which are setup to be ready to receive an interrupt which is being delivered in 1 of N mode. In order to prepare a PE to take a 1 of N routed interrupt, that PE must be configured as follows:
See section 3.3.2, which I could not understand.
 
* GICR_WAKER.ProcessorSleep == 0, and the interrupt group of the interrupt must be enabled on that PE.
* GICD_CTLR.E1NWF == 1.
* GICR_TYPER.DPGS == 1. (DPGS = Disable Processor Group Selections). Furthermore, GICR_CTLR.{DPG1S, DPG1NS, DPG0} == 0.
 
= IntIDs =
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* [[http://www.wiki.xilinx.com/GIC|Xilinx GIC Wiki page]]
* [[http://ssup2.iptime.org/wiki/ARM_Generic_Interrupt_Controller_(GIC)| Another Wiki page]]
 
[[Category:ARM]]
[[Category:Interrupts]]
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