Exceptions: Difference between revisions

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'''Exceptions''' as described in this article are generated by the CPU when an 'error' occurs. Some exceptions are not really errors in most cases, such as [[#Page Fault|page faults]]. Exceptions are a type of [[interrupt]].
 
Exceptions are classified as:
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| No
|-
! [[#Non-maskable Maskable Interrupt|Non-maskable Interrupt]]
| 2
| Interrupt
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===== Error code =====
The Invalid TSS exception sets an error code, which is either a TSS selector index, LDT selector index or[[#Selector segmentError Code|selector index]].
 
==== Segment Not Present ====
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===== Error code =====
The Segment Not Present exception sets an error code, which is the [[#Selector Error Code|segment selector index]] of the segment descriptor which caused the exception.
 
==== Stack-Segment Fault ====
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===== Error code =====
The Stack-Segment Fault sets an error code, which is stack [[#Selector Error Code|segment selector index]] when a non-present segment descriptor was referenced. Otherwise, 0.
 
==== General Protection Fault ====
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===== Error code =====
The General Protection Fault sets an error code, which is stack [[#Selector Error Code|segment selector index]] when the exception is segment related. Otherwise, 0.
 
==== Page Fault ====
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! Name
! Description
|-valign="top"
|-
!align="left"| P
! P
| 1 bit
| Present
| When set, the page fault was caused by a page-protection violation. When not set, it was caused by a non-present page.
|-valign="top"
|-
!align="left"| W
! W
| 1 bit
| Write
| When set, the page fault was caused by a page write. When not set, it was caused by a page read.
|-valign="top"
|-
!align="left"| U
! U
| 1 bit
| User
| When set, the page fault was caused while CPL = 3. This does not necessarily mean that the page fault was a privilege violation.
|-valign="top"
|-
!align="left"| R
! R
| 1 bit
| Reserved write
| When set, the page fault was caused by reading a 1 in a reserved field.
|-valign="top"
|-
!align="left"| I
! I
| 1 bit
| Instruction Fetch
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The saved instruction pointer points to the instruction which is about to be executed when the exception occurred. The x87 instruction pointer register contains the address of the last instruction which caused the exception.
 
===== Error Code =====
The exception does not set an error code. However, exception information is available in the x87 status word register.
 
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The saved instruction pointer points to the instruction which caused the exception.
 
===== Error Code =====
The exception does not set an error code. However, exception information is available in the MXCSR register.
 
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==== Triple Fault ====
{{main|Triple Fault}}
The Triple Fault is not really an exception, because it does not have an associated vector number. Nonetheless, a triple fault occurs when an exception is generated inside the double fault exception handler. It usually results in the processor resetting. See the main article for more information about possible causes and how to avoid them.
{{stub}}
 
=== MiscSelector Error Code ===
<pre>
==== Non-maskable Interrupt ====
31 16 15 3 2 1 0
{{stub}}
+---+-- --+---+---+-- --+---+---+---+---+
| Reserved | Index | Tbl | E |
+---+-- --+---+---+-- --+---+---+---+---+
</pre>
 
{| {{wikitable}}
!
! Length
! Name
! Description
|-valign="top"
!align="left"| E
| 1 bit
| External
| When set, the exception originated externally to the processor.
|-valign="top"
!align="left"| Tbl
| 2 bits
| IDT/GDT/LDT table
| This is one of the following values:
{| {{wikitable}}
! Value
! Description
|-
! 0b00
| The Selector Index references a descriptor in the GDT.
|-
! 0b01
| The Selector Index references a descriptor in the IDT.
|-
! 0b10
| The Selector Index references a descriptor in the LDT.
|-
! 0b11
| The Selector Index references a descriptor in the IDT.
|-}
 
|-valign="top"
!align="left"| Index
| 13 bits
| Selector Index
| The index in the GDT, IDT or LDT.
|}
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