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Exceptions: Difference between revisions
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Exceptions are classified as:
* '''Faults''': These can be corrected and the program may continue as if nothing
* '''Traps''': Traps are reported immediately after the execution of the trapping instruction.
* '''Aborts''': Some severe unrecoverable error.
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The Invalid Opcode exception occurs when the processor tries to execute an invalid or undefined opcode, or an instruction with invalid prefixes.
The saved instruction pointer
==== Device Not Available ====
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An Invalid TSS exception occurs when an invalid segment selector is referenced as part of a task which, or as a result of a control transfer through a gate descriptor, which results in an invalid stack-segment reference using an SS selector in the TSS.
When the exception
===== Error code =====
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==== Segment Not Present ====
The Segment Not Present exception
However wen loading a stack-segment selector which references a descriptor which is not present, a [[#Stack-Segment Fault|Stack-Segment Fault]] occurs.
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==== x87 Floating-Point Exception ====
The x87 Floating-Point Exception occurs when the FWAIT or WAIT instruction, or any waiting floating-point instruction is executed, and the following conditions are true:
* [[CR0|CR0.NE]] is 1;
* an unmasked x87 floating point exception is pending (i.e. the exception bit in the x87 floating point status-word register is set to 1).
The saved instruction pointer points to the instruction which is about to be executed when the exception occurred. The x87 instruction pointer register contains the address of the last instruction which caused the exception.
===== Error Code ====
The exception does not set an error code. However, exception information is available in the x87 status word register.
==== Alignment Check ====
An Alignment Check exception occurs when alignment checking is enabled and an unaligned memory data reference is performed. Alignment checking is only performed in CPL 3.
Alignment checking is disabled by default. To enable it, set the [[CR0|CR0.AM]] and [[RFLAGS|RFLAGS.AC]] bits both to 1.
The saved instruction pointer points to the instruction which caused the exception.
==== SIMD Floating-Point Exception ====
The SIMD Floating-Point Exception occurs when an unmasked 128-bit media floating-point exception occurs and the [[CR4|CR4.OSXMMEXCPT]] bit is set to 1.
The saved instruction pointer points to the instruction which caused the exception.
===== Error Code ====
The exception does not set an error code. However, exception information is available in the MXCSR register.
=== Traps ===
==== Debug ====
The Debug exception occurs on the following conditions:
* Instruction fetch breakpoint (Fault)
* General detect condition (Fault)
* Data read or write breakpoint (Trap)
* I/O read or write breakpoint (Trap)
* Single-step (Trap)
* Task-switch (Trap)
When the exception is a fault, the saved instruction pointer points to the instruction which caused the exception. When the exception is a trap, the saved instruction pointer points to the instruction after the instruction which caused the exception.
===== Error code =====
The Debug exception does not set an error code. However, exception information is provided in the debug registers.
==== Breakpoint ====
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==== Machine Check ====
The Machine Check exception is model specific and processor implementations are not required to support it. It uses model-specific registers to provide error information. It is disabled by default. To enable it, set the [[CR4|CR4.MCE]] bit to 1.
The value of the saved instruction pointer depends on the implementation and the exception.
==== Triple Fault ====
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