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Exceptions: Difference between revisions
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'''Exceptions''', as described in this article, are a type of [[interrupt]] generated by the CPU when an 'error' occurs. Some exceptions are not really errors in most cases, such as [[#Page Fault|page faults
Exceptions are classified as:
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* '''Traps''': Traps are reported immediately after the execution of the trapping instruction.
* '''Aborts''': Some severe unrecoverable error.
Some exceptions will push a 32-bit "error code" on to the top of the stack, which provides additional information about the error. This value must be pulled from the stack before returning control back to the currently running program (i.e. before calling IRET). In [[Long Mode]], the error code is padded with zeros to form a 64-bit push, so that it can be popped like any other value.
{| {{wikitable}}
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! Error code?
|-
! [[#
| 0 (0x0)
| Fault
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| Abort
| #DF
| Yes (Zero)
|-
! <strike>[[#Coprocessor Segment Overrun|Coprocessor Segment Overrun]]</strike>
| 9 (0x9)
| Fault
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| #VE
| No
! [[#Control Protection Exception|Control Protection Exception]]
| 21 (0x15)
| Fault
| #CP
| Yes
|-
! Reserved
|
| -
| -
| No
|-
! [[#Hypervisor Injection Exception|Hypervisor Injection Exception]]
| 28 (0x1C)
| Fault
| #HV
| No
|-
! [[#VMM Communication Exception|VMM Communication Exception]]
| 29 (0x1D)
| Fault
| #VC
| Yes
|-
! [[#Security Exception|Security Exception]]
| 30 (0x1E)
|
| #SX
|
|-
! Reserved
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| No
|-
! <strike>[[#FPU Error
|
| Interrupt
▲| -
|
| No
|}
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=== Faults ===
====
The '''
The saved instruction pointer points to the DIV or IDIV instruction which caused the exception.
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==== Invalid Opcode ====
The Invalid Opcode exception occurs when the processor tries to execute an invalid or undefined opcode, or an instruction with invalid prefixes. It also occurs
* The instruction length exceeds 15 bytes, but this only occurs with redundant prefixes.
* The instruction tries to access a non-existent control register (for example, <code>mov cr6, eax</code>).
* The UD instruction is executed.
The saved instruction pointer points to the instruction which caused the exception.
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==== Invalid TSS ====
An Invalid TSS exception occurs when an invalid segment selector is referenced as part of a task
When the exception occurred before loading the segment selectors from the TSS, the saved instruction pointer points to the instruction which caused the exception. Otherwise, and this is more common, it points to the first instruction in the new task.
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==== Segment Not Present ====
The Segment Not Present exception occurs when trying to load a segment or gate which has
However when loading a stack-segment selector which references a descriptor which is not present, a [[#Stack-Segment Fault|Stack-Segment Fault]] occurs.
If the exception happens during a hardware task switch, the segment values should not be relied upon by the handler. That is, the handler should check them before trying to resume the new task. There are three ways to do this, according to the Intel documentation.
The saved instruction pointer points to the instruction which caused the exception.
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* When the stack-limit check fails.
If the exception happens during a hardware task switch, the segment values should not be relied upon by the handler. That is, the handler should check them before trying to resume the new task. There are three ways to do this, according to the Intel documentation.
The saved instruction pointer points to the instruction which caused the exception, unless the fault occurred because of loading a non-present stack segment during a hardware task switch, in which case it points to the next instruction of the new task.
'''Error code:''' The Stack-Segment Fault sets an error code, which is the stack [[#Selector Error Code|segment selector index]] when a non-present segment descriptor was referenced or a limit check failed during a hardware task switch. Otherwise (for present segments and already in use), the error code is 0.
==== General Protection Fault ====
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* Segment error (privilege, type, limit, read/write rights).
* Executing a privileged instruction while CPL != 0.
* Writing a 1 in a reserved register field or writing invalid value combinations (e.g. CR0 with PE=0 and PG=1).
* Referencing or accessing a null-descriptor.
* Accessing a memory address with bits 48-63 not matching bit 47 (e.g. 0x_0000_8000_0000_0000 instead of 0x_ffff_8000_0000_0000) in 64 bit mode.
The saved instruction pointer points to the instruction which caused the exception.
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==== Page Fault ====
A Page Fault occurs when:
* A [[Paging|page directory or table]] entry is not present in physical memory.
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<pre>
31 15 4 0
+---+-- --+---+-----+---+-- --+---+----+----+---+---+---+---+---+
| Reserved | SGX | Reserved | SS | PK | I | R | U | W | P |
+---+-- --+---+-----+---+-- --+---+----+----+---+---+---+---+---+
</pre>
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| 1 bit
| Write
| When set, the page fault was caused by a
|-valign="top"
!align="left"| U
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| 1 bit
| Reserved write
| When set, one or more page directory entries contain reserved bits which are set to 1. This only applies when the PSE or PAE flags in CR4 are set to 1.
| When set, the page fault was caused by reading a 1 in a reserved field.▼
|-valign="top"
!align="left"| I
| 1 bit
| Instruction Fetch
| When set, the page fault was caused by an instruction fetch. This only applies when the No-Execute bit is supported and enabled.
|-valign="top"
!align="left"| PK
| 1 bit
| Protection key
| When set, the page fault was caused by a protection-key violation. The PKRU register (for user-mode accesses) or PKRS MSR (for supervisor-mode accesses) specifies the protection key rights.
|-valign="top"
!align="left"| SS
| 1 bit
| Shadow stack
|-valign="top"
!align="left | SGX
| 1 bit
| Software Guard Extensions
| When set, the fault was due to an [https://en.wikipedia.org/wiki/Software_Guard_Extensions SGX violation]. The fault is unrelated to ordinary paging.
|}
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When the exception is a fault, the saved instruction pointer points to the instruction which caused the exception. When the exception is a trap, the saved instruction pointer points to the instruction after the instruction which caused the exception.
'''Error code:''' The Debug exception does not set an error code. However, exception information is provided in the debug registers ([[CPU_Registers_x86#Debug_Registers]]).
==== Breakpoint ====
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==== Double Fault ====
A Double Fault occurs when an exception is unhandled or when an exception occurs while the CPU is trying to call an exception handler. Normally, two exception at the same time are handled one after another, but in some cases that is not possible. For example, if a page fault occurs, but the exception handler is located in a not-present page, two page faults would occur and neither can be handled. A double fault would occur.
A double fault will always generate an error code with a value of zero.
The saved instruction pointer is undefined. A double fault cannot be recovered. The faulting process must be terminated.
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=== Legacy ===
The following exceptions happen on outdated technology, but are no longer used or should be avoided. They apply mostly to the intel 386 and earlier, and might include CPUs from other manufacturers around the same time.
====FPU Error Interrupt====
In the old days, the floating point unit was a dedicated chip that could be attached to the processor. It lacked direct wiring of FPU errors to the processor, so instead it used [[PIC|IRQ 13]], allowing the CPU to deal with errors at
====Coprocessor Segment Overrun====
When the FPU was still external to the processor, it had separate segment checking in protected mode. Since the 486 this is handled by a [[#General Protection Fault|GPF]] instead like it already did with non-FPU memory accesses.
== See Also ==
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* [http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf Intel® 64 and IA-32 Architectures Software Developer's Manual], Volume 3 (System Programming Guide), Chapter 6 (Interrupt and exception handling)
[[Category:X86]]
[[Category:Interrupts]]
[[de:Exception]]
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