EXtensible Host Controller Interface: Difference between revisions

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{{DISPLAYTITLE:eXtensible Host Controller Interface}}
eXtensible Host Controller Interface (xHCI) defines a register-level description of a Host Controller for Universal Serial bus ([[USB]]), which is capable of interfacing to USB 1.x, 2.0, and 3.0 compatible devices without the use of companion controllers.
 
== Technical Details ==
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|-
| 00 || CAPLENGTH || Capability Register Length
|-
| 01 || RSVD || Reserved
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| 02 || HCIVERSION || Interface Version Number
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| 0C || HCSPARAMS3 || Structural Parameters 3
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| 10 || HCCPARAMSHCCPARAMS1 || Capability Parameters
|-
| 14 || DBOFF || Doorbell Offset
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| 18 || RTSOFF || Runtime Registers Space Offset
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| 1C || HCCPARMS2 || Capability Parameters 2
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|}
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Reading CRCR (or bits of it) provides '0'. Therefore, keep your own track of this address. Bit 0 of CRCR is the Consumer Cycle State (CCS) flag.
 
== Port Registers ==
 
AfterAt the end of the operational registers ('''at offset 0x400!'''), each port on the root hub is assigned a set of registers. The number of entries in the port registers table is determined by the MaxPorts value in the HCSPARAMS1 register.
 
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The xHCI specifications support "virtual" controllers that can be used to support multiple virtual machines running on a single physical machine. These registers must be configured and managed by the VM host, and effectively duplicate the registers above for use by the guest VMs.
 
== Chipsets with both EHC and xHC ==
 
Some chipsets such as the Intel Panther Point (<code>8086:1e31</code>) feature both an EHC and xHC. Both controllers share the same set of ports and access to each port is determined by a hardware toggle (0 = EHC, 1 = xHC).
 
To switch a port to either the EHC or the xHC registers <code>USB3_PSSEN</code> (<code>0xd0</code>) and <code>XUSB2PR</code> (<code>0xd8</code>) must be written.
 
For example, to switch all available ports to the xHC (make sure the registers are actually present!):
 
<syntaxhighlight lang="C">
#define USB3_PSSEN 0xd0
#define XUSB2PR 0xd8
 
char *pci_header = ...;
(u32 *)(pci_header + USB3_PSSEN) = 0xffff_ffff; // Enable SuperSpeed on USB3 ports
(u32 *)(pci_header + XUSB2PR) = 0xffff_ffff; // Switch over USB2 ports
</syntaxhighlight>
 
== External Links ==
 
*[https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf eXtensible Host Controller Interface Specification 1.2]
* Commit <code>69e848c2090aebba5698a1620604c7dccb448684</code> in the Linux source tree
*[https://github.com/haiku/haiku/blob/master/src/add-ons/kernel/busses/usb/xhci.cpp Haiku's XHCI implementation]
 
[[Category:USB]]