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Context Switching: Difference between revisions
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When the CPU changes to a higher privilege level (CPL 0 being the highest) it will load new values for SS and ESP from the [[Task State Segment]] (TSS). '''If the operating system uses multiple privilege levels it must create and load a TSS'''. An interrupt generated while the processor is in ring 3 will switch the stack to the resulting permission level stack entry in the TSS. During a software context switch the values for SS0:ESP0 (and possibly SS1:ESP1 or SS2:ESP2) will need to be set in the TSS. If the processor is operating in [[Long Mode]], the stack selectors are no longer present and the RSP0-2 fields are used to provide the destination stack address.
If a context switch also entails a change in IO port permissions, a different TSS may be loaded for each [[wikipedia:Process_(computing)|Process]]. When running virtual 8086 tasks, the IO permission map in the TSS isn't checked to provide I/O port protection. IO protection can be implemented by setting the IO Permission Level to 0. This will generate a [[Exceptions#General_Protection_Fault|General Protection Fault]] when a process in ring 3 attempts to write to or read from an IO port. The GP fault handler can then check permissions and carry out the port IO on behalf of the user-mode code.
===Other Possibilities===
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