Anonymous user
Chip Numbers, Acronyms and Things: Difference between revisions
m
s/dword/uint32_t/g
| [unchecked revision] | [unchecked revision] |
No edit summary |
m (s/dword/uint32_t/g) |
||
| (8 intermediate revisions by 4 users not shown) | |||
Line 3:
;8048:Controller chip in the XT keyboard
;82072A:Controller chip in the AT floppy disk drive
;
;82284:The 80286 clock generator
;82288:The 80286 bus controller chip
;8237A:An
;
;82489DX:The original Advanced Programmable Interrupt Controller (APIC) used in
;8253:Programmable Interval Timer ([[PIT]]) chip in the XT
;8254:Programmable Interval Timer ([[PIT]]). Used in AT's and EISA/MCA machines. Just an improved version of the 8253.
;8259A:Programmable Interrupt Controller ([[PIC]]) used in all non-SMP PC's that predate
;8284:Clock generator in the 8088/8086/80186
;8288:Bus controller in the 8088/8086/80186
;8741:Common controller chip in AT keyboards
;8742:Controller chip in
;ABIOS:Advanced BIOS.
;ARLL:Advanced RLL. Method used in Hard Disks. MFM, RLL, etc.
;ASPI:Advanced SCSI Programming Interface. An
;ATA:AT Attachment.
;BIST:Built
;Booting:The loading of the BIOS and kicking in the bootsector to bootstrap an OS loader.
;Bootstrap:The bootstrap is a small program that loads an operating system. (Usually synonymous with the bootsector/MBR). Also used to describe the process of setting up a compiler on a new system not having one already.
Line 26:
;Call Gate:Much like an software driven interrupt, a call gate allows access to other code from a different privilege level.
;Combicontroller:Combine a Floppy disk controller chip and a Hard disk controller chip and you have a combicontroller. It is not limited to just floppy+hard drive chips. Usually meant to refer to the actual plug-in card where you have two floppy and two hd IDE ports.
;CPL:Current privilege level. The current [[Protected Mode|ring]] in which code is being executed.
;Descriptor:An 8 byte structure that describes a segment/gate/task in protected mode.
;DMA:[[DMA|Direct Memory Access]]. Allows peripheral devices to access main memory directly, bypassing the CPU.
;DPL:Descriptor privilege level. The privilege needed to use a descriptor in the [[GDT]] or [[IDT]]
;EISA:Extended ISA. Basically extends the ISA bus from being
;ESDI:Enhanced Small Device Interface. A hard disk controlling mechanism. Successor to the ST506/412 interface. Can handle pumping data out at 24mbits (3mb a second)
;Exception:CPU error. Usually hardware triggered, but can also be software triggered (some debug breakpoints, etc)
;Expanded Memory:Memory used by an EMS driver. Located beyond 1mb mark.
;Extended Memory:Memory used by an XMS driver. Located beyond the 1mb mark. The first 64kb of XMS is known as HMA (High Memory Area).
;Fault:An exception that is
;FDC:Floppy Disk Controller
;FIFO:First In First Out. FIFO buffers are common in newer UART chips for communications (
;GDT:Global Descriptor Table. This table contains descriptors that are potentially available to all programs in protected mode.
;HAL:Hardware Abstraction Layer. Used by
;HDC:Hard Disk Controller
;IDE:Intelligent Drive Electronics.
;IDT:Interrupt Descriptor Table. Table of
;Interrupt:Interrupts can be software or hardware generated. When an interrupt occurs, the CPU jumps to code assigned to be ran whenever that interrupt is triggered.
;Interrupt Gate:A descriptor for calling an interrupt.
;IRQ:Interrupt Request. Hardware signal to the CPU from an external peripheral.
;ISA:Industry Standard Architecture. The defined
;LDT:Local Descriptor Table. A table of descriptors that can only be accessed by the task that owns the LDT and none other.
;MC146818:CMOS
;MMU:Memory Management Unit. The MMU is often contained within the CPU but can be external to the CPU. eg: old 68k CPU's did not have an MMU but one could be attached externally. The MMU is responsible for doing things like address segmentation translation and paging.
;PD765:The floppy controller chip in the XT
;Multitasking:Where the CPU 'appears' to be running several tasks all at the same time.
;NMI:[[Non Maskable Interrupt]]. An interrupt request sent to the CPU that must be dealt with immediately.▼
▲;Nibble,Nybble:Group of 4 bits. Half a byte... Quarter a word... Eigth of a dword... etc..
▲;NMI:Non Maskable Interrupt. An interrupt request sent to the CPU that must be dealt with immediately.
;Page:Section of memory that is classed as a single entity. eg: x86 in pmode has pages of 1byte, 4kb and 4mb in size.
;Page Directory:Holds the entries for the paging table mechanism. Unlike Page Tables, the Page Directory can't be swapped out of memory.
;PCI:Peripheral Component Interconnect. A Local Bus standard running at 32bits at 33mhz (can go higher). PCI has replaced ISA as the most common bus interface for
;PCMCIA:Personal Computer Memory Card International Association. Small credit card sized units that plug into portable computer PCMCIA slot and provide things like extra memory, modems, etc.
;PIC:Programmable Interrupt Controller. The PIC manages hardware interrupts.
;PIT:Programmable Interval Timer. The PIT is like a stopwatch with periodic alarm...
;POST:Power On Self Test. Your computer does this when you turn it on in order to assess that its 100% A-OK and can boot up without error.
;RPL:Requested Privilege Level. Used in [[Protected Mode]] to pretend running at a lower privilege level for accessing a descriptor.
;RTC:Real Time Clock
;SCSI:Small Computer Systems Interface. A different method from ATA/IDE for connecting devices to your computer.
Line 68 ⟶ 70:
;Trap:An exception which occurs AFTER the error has occurred instead of before (see Fault).
;TSS:Task State Segment. A data structure that holds the state of the CPU when for that task. Used by multitasking OS.
;
[[Category:Resources]]
| |||