CPU Registers x86: Difference between revisions

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Bot: Replace deprecated source tag with syntaxhighlight
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(→‎CR4: Added link to Supervisor Memory Protection)
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NOTE: This register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
<sourcesyntaxhighlight lang="asm">
; First way:
; Write:
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; Read:
smsw reg
</syntaxhighlight>
</source>
 
====CR1====
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| Page-level Write-Through
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 4
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| Page-level Cache Disable
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 12-31 (63)
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| Page Directory Base Register
| Base of PDPT
| Base of PML4T/PML5T
|-
|}
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Reserved, same case as CR1.
 
====CR8====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0-3
| TPL
| Task Priority Level
|-
|}
 
==Extended Control Registers==
 
====XCR0====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0
| X87
| x87 FPU/MMX support (must be 1)
|-
| 1
| SSE
| XSAVE support for MXCSR and XMM registers
|-
| 2
| AVX
| AVX enabled and XSAVE support for upper halves of YMM registers
|-
| 3
| BNDREG
| MPX enabled and XSAVE support for BND0-BND3 registers
|-
| 4
| BNDCSR
| MPX enabled and XSAVE support for BNDCFGU and BNDSTATUS registers
|-
| 5
| opmask
| AVX-512 enabled and XSAVE support for opmask registers k0-k7
|-
| 6
| ZMM_Hi256
| AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers
|-
| 7
| Hi16_ZMM
| AVX-512 enabled and XSAVE support for upper ZMM registers
|-
| 9
| PKRU
| XSAVE support for PKRU register
|-
|}
 
XCR0 can only be accessed if bit 18 of CR4 is set to 1. XGETBV and XSETBV instructions are used to access XCR0.
 
==Debug Registers==
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{| {{wikitable}}
|-
! NitsBits
! Label
! Description
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Stores the segment selector of the [[IDT]].
 
[[Category:X86 CPU]]
[[Category:CPU_Registers]]