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CPU Registers x86: Difference between revisions

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CPU Registers x86 (view source)

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== General Purpose Registers ==
[[Category:CPU_Registers]]
 
==General Purpose Registers==
 
{| {{wikitable}}
|-
! 32 64-bit
! 16 32-bit
! 8 high 16-bit
! 8 lowhigh bitbits
! 8 low bits
! description
! Description
|-
| eaxRAX
| axEAX
| ahAX
| alAH
| AL
| accumulator
| Accumulator
|-
| ebxRBX
| bxEBX
| bhBX
| blBH
| baseBL
| Base
|-
| ecxRCX
| cxECX
| chCX
| clCH
| counterCL
| Counter
|-
| edxRDX
| dxEDX
| dhDX
| dlDH
| dataDL
| Data
|-
| RSI
|}
| ESI
 
| SI
==Segment Registers==
| N/A
 
| SIL
{| {{wikitable}}
| Source
|-
| RDI
! 16 bit
| EDI
! description
| DI
| N/A
| DIL
| Destination
|-
| csRSP
| ESP
| code segment
| SP
| N/A
| SPL
| Stack Pointer
|-
| dsRBP
| EBP
| data segment
|- BP
| N/A
| es, fs, gs
| BPL
| extra segment
| Stack Base Pointer
|-
| ss
| stack segment
|-
|}
 
==Index Pointer Registers ==
 
{| {{wikitable}}
|-
! 32 64-bit
! 16 32-bit
! 16-bit
! description
! Description
|-
| esi
| si
| source index
|-
| ediRIP
| diEIP
| IP
| destination index
| Instruction Pointer
|-
|}
 
==Pointer Segment Registers ==
 
{| {{wikitable}}
|-
! 32 16-bit
! Description
! 16 bit
! description
|-
| ebpCS
| Code Segment
| bp
| base pointer
|-
| espDS
| Data Segment
| sp
| stack pointer
|-
| eipES
| Extra Segment
|
|-
| instruction pointer
| SS
| Stack Segment
|-
| FS
| General Purpose F Segment
|-
| GS
| General Purpose G Segment
|-
|}
 
== EFLAGS Register ==
 
{| {{wikitable}}
|-
! bitBit
! labelLabel
! Description
! description
|-
| 0
| cfCF
| carryCarry flag
|-
| 2
| pfPF
| parityParity flag
|-
| 4
| afAF
| auxiliaryAuxiliary flag
|-
| 6
| zfZF
| zeroZero flag
|-
| 7
| sfSF
| signSign flag
|-
| 8
| tfTF
| trapTrap flag
|-
| 9
| ifIF
| interruptInterrupt enable flag
|-
| 10
| dfDF
| directionDirection flag
|-
| 11
| ofOF
| overflowOverflow flag
|-
| 12-13
| ioplIOPL
| iI/oO priviledgeprivilege level
|-
| 14
| ntNT
| nestedNested task flag
|-
| 16
| rfRF
| resumeResume flag
|-
| 17
| vmVM
| virtualVirtual 8086 mode flag
|-
| 18
| acAC
| alignmentAlignment check flag
|-
| 19
| vifVIF
| virtualVirtual interrupt flag
|-
| 20
| vipVIP
| virtualVirtual interrupt pending
|-
| 21
| idID
| Able to use CPUID instruction
| id flag
|-
|}
 
Unlisted bits are reserved.
 
==Control Registers==
Line 182 ⟶ 197:
{| {{wikitable}}
|-
! bitBit
! labelLabel
! Description
! description
|-
| 0
| pePE
| Protected Mode Enable
| protected mode enable
|-
| 1
| mpMP
| monitorMonitor co-processor
|-
| 2
| emEM
| x87 FPU Emulation
| emulation
|-
| 3
| tsTS
| taskTask switched
|-
| 4
| etET
| extensionExtension type
|-
| 5
| neNE
| numericNumeric error
|-
| 16
| wpWP
| writeWrite protect
|-
| 18
| amAM
| alignmentAlignment mask
|-
| 29
| nwNW
| notNot-write through
|-
| 30
| cdCD
| cacheCache disable
|-
| 31
| pgPG
| pagingPaging
|-
|}
NOTE: that thisThis register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
<sourcesyntaxhighlight lang="asm">
; First way:
;way 1:
;write Write:
mov cr0,reg32(64) reg
;read:
mov reg32(64),cr0
;----------------------
;way 2:
;write:
lmsw reg16(32/64) ; the 'w' in lms(w) stands for word size (16 bit) but the instruction itself can modify the upper 48 bit of cr0 using instruction overrides.
 
;read Read:
mov reg, cr0
smsw reg16(32/64) ; SAME as above
; ----------------------
</source>
; Second way:
; Write:
lmsw reg
 
; Read:
smsw reg
</syntaxhighlight>
 
====CR1====
 
Reserved, the CPU will throw a #UD exception when trying to access it.
Reserved
 
====CR2====
Line 255 ⟶ 271:
{| {{wikitable}}
|-
! bitBit
! labelLabel
! Description
! description
|-
| 0-31 (63)
| pflaPFLA
| Page Fault Linear Address
| page fault linear address
|-
|}
Line 269 ⟶ 285:
{| {{wikitable}}
|-
! bitBit
! Label
! description
! Description
! [[PAE]] mode
! [[Long Mode|long modePAE]]
! [[Long Mode]]
|-
| 3
| PWT
| Page-level Write-Through
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 4
| PCD
| Page-level Cache Disable
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 012-31 (63)
| PDBR
| physical base address of page directory
| Page Directory Base Register
| base of PDPT
| baseBase of PML4TPDPT
| Base of PML4T/PML5T
|-
|}
Bits 0-11 of the physical base address are assumed to be 0. Bits 3 and 4 of CR3 are only used when accessing a PDE in 32-bit paging without PAE.
Note that this must be page aligned
 
====CR4====
Line 286 ⟶ 316:
{| {{wikitable}}
|-
! bitBit
! labelLabel
! Description
! description
|-
| 0
| vmeVME
| virtualVirtual 8086 modeMode extensionsExtensions
|-
| 1
| pviPVI
| protected Protected-mode virtualVirtual interruptsInterrupts
|-
| 2
| tsdTSD
| Time Stamp Disable
| time stamp disable
|-
| 3
| deDE
| Debugging Extensions
| debugging extensions
|-
| 4
| psePSE
| Page Size Extension
| page size extension
|-
| 5
| paePAE
| Physical Address Extension
| physical address extension
|-
| 6
| mceMCE
| Machine Check Exception
| machine check exception
|-
| 7
| pgePGE
| Page Global Enabled
| page global enable
|-
| 8
| pcePCE
| Performance-Monitoring Counter enable
| performance monitoring counter enable
|-
| 9
| osfxsrOSFXSR
| osOperating system support for fxsaveFXSAVE and fxrstorFXRSTOR instructions
|-
| 10
| OSXMMEXCPT
| osxmmexcpt
| Operating System Support for Unmasked SIMD Floating-Point Exceptions
| os support for unmasked simd floating point exceptions
|-
| 11
| UMIP
| User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
|-
| 13
| vmxeVMXE
| Virtual Machine Extensions Enable
| virtual machine extensions enable
|-
| 14
| smxeSMXE
| Safer Mode Extensions Enable
| safer mode extensions enable
|-
| 16
| FSGSBASE
| Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
|-
| 17
| pcidePCIDE
| pcidPCID enableEnable
|-
| 18
| osxsaveOSXSAVE
| xsaveXSAVE and processorProcessor extendedExtended statesStates enableEnable
|-
| 20
| smepSMEP
| [[Supervisor Memory Protection|Supervisor Mode Execution Protection]] Enable
| supervisor mode executions protection enable
|-
| 21
| smapSMAP
| [[Supervisor Memory Protection|Supervisor Mode Access Prevention]] Enable
| supervisor mode access protection enable
|-
| 22
| PKE
| Protection Key Enable
|-
| 23
| CET
| Control-flow Enforcement Technology
|-
| 24
| PKS
| Enable Protection Keys for Supervisor-Mode Pages
|-
|}
 
====CR5 - CR7====
 
Reserved, same case as CR1.
 
====CR8====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0-3
| TPL
| Task Priority Level
|-
|}
 
==Extended Control Registers==
 
====XCR0====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0
| X87
| x87 FPU/MMX support (must be 1)
|-
| 1
| SSE
| XSAVE support for MXCSR and XMM registers
|-
| 2
| AVX
| AVX enabled and XSAVE support for upper halves of YMM registers
|-
| 3
| BNDREG
| MPX enabled and XSAVE support for BND0-BND3 registers
|-
| 4
| BNDCSR
| MPX enabled and XSAVE support for BNDCFGU and BNDSTATUS registers
|-
| 5
| opmask
| AVX-512 enabled and XSAVE support for opmask registers k0-k7
|-
| 6
| ZMM_Hi256
| AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers
|-
| 7
| Hi16_ZMM
| AVX-512 enabled and XSAVE support for upper ZMM registers
|-
| 9
| PKRU
| XSAVE support for PKRU register
|-
|}
====CR(1, 5->7)====
 
XCR0 can only be accessed if bit 18 of CR4 is set to 1. XGETBV and XSETBV instructions are used to access XCR0.
Reserved, the cpu will throw a #ud exeption when trying to access them.
 
==Debug Registers==
Line 371 ⟶ 484:
====DR6====
 
It permits the debugger to determine which debug conditions have occurred. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.<br>
Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.<br>
Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.<br>
Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).<br>
Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.<br>
Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.<br>
 
====DR7====
Line 377 ⟶ 495:
{| {{wikitable}}
|-
! bitBit
! Description
! description
|-
| 0
| localLocal DR0 breakpoint
|-
| 1
| globalGlobal DR0 breakpoint
|-
| 2
| localLocal DR1 breakpoint
|-
| 3
| globalGlobal DR1 breakpoint
|-
| 4
| localLocal DR2 breakpoint
|-
| 5
| globalGlobal DR2 breakpoint
|-
| 6
| localLocal DR3 breakpoint
|-
| 7
| globalGlobal DR3 breakpoint
|-
| 16-17
| conditionsConditions for DR0
|-
| 18-19
| sizeSize of DR0 breakpoint
|-
| 20-21
| conditionsConditions for DR1
|-
| 22-23
| sizeSize of DR1 breakpoint
|-
| 24-25
| conditionsConditions for DR2
|-
| 26-27
| sizeSize of DR2 breakpoint
|-
| 28-29
| conditionsConditions for DR3
|-
| 30-31
| sizeSize of DR3 breakpoint
|-
|}
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
00bCondition condition00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).
 
==Test Registers==
Line 436 ⟶ 554:
{| {{wikitable}}
|-
! nameName
! Description
! description
|-
| TR3 - TR5
| Undocumented
| undocumented
|-
| TR6
| testTest command register
|-
| TR7
| testTest data register
|-
|}
Line 456 ⟶ 574:
{| {{wikitable}}
|-
! bitsBits
! labelLabel
! Description
! description
|-
| 0-15
| limitLimit
| (sizeSize of [[GDT]]) - 1
|-
| 16-47
| baseBase
| startingStarting address of [[GDT]]
|-
|}
 
Stores the segment selector of the [[GDT]].
 
====LDTR====
 
{| {{wikitable}}
! Bits
! Label
! Description
|-
| 0-15
| Limit
| (Size of [[LDT]]) - 1
|-
| 16-47
| Base
| Starting address of [[LDT]]
|-
|}
 
Stores the segment selector of the [[LDT]].
Line 477 ⟶ 612:
 
{| {{wikitable}}
! bitsBits
! labelLabel
! Description
! description
|-
| 0-15
| limitLimit
| (sizeSize of [[IDT]]) - 1
|-
| 16-47
| baseBase
| startingStarting address of [[IDT]]
|-
|}
 
Stores the segment selector of the [[IDT]].
 
[[Category:X86 CPU]]
[[Category:CPU_Registers]]
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