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== General Purpose Registers ==
{| {{wikitable}}
|-
!
!
!
! 8
! 8 low bits
! Description
|-
|
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| AL
| Accumulator
|-
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| Base
|-
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| Counter
|-
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| Data
|-
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| SI
| N/A
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| Source
|-
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| DI
| N/A
|
| Destination
|-
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| SP
| N/A
|
| Stack Pointer
|-
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| N/A
| BPL
| Stack Base Pointer
|-
|}
== Pointer Registers ==
{| {{wikitable}}
|-
!
!
! 16-bit
! Description
|-
|
|
| IP
| Instruction Pointer
|-
|}
== Segment Registers ==
{| {{wikitable}}
|-
! 16
! Description
|-
|
|
|-
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|
|-
|
| Extra Segment
|-
|
| Stack Segment
|-
|
| General Purpose F Segment
|-
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| General Purpose G Segment
|-
|}
== EFLAGS Register ==
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
|
|
|-
| 2
|
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|-
| 4
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|-
| 6
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|-
| 7
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|-
| 8
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|-
| 9
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|-
| 10
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|-
| 11
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|-
| 12-13
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|-
| 14
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|-
| 16
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|-
| 17
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|-
| 18
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|-
| 19
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|-
| 20
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|-
| 21
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| Able to use CPUID instruction
|-
|}
Unlisted bits are reserved.
==Control Registers==
Line 186 ⟶ 197:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
|
| Protected Mode Enable
|-
| 1
|
|
|-
| 2
|
| x87 FPU Emulation
|-
| 3
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|-
| 4
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|-
| 5
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|-
| 16
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|-
| 18
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|-
| 29
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|-
| 30
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|-
| 31
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|-
|}
NOTE:
<
; First way:
;
mov cr0, reg
; Read:
mov reg, cr0
; ----------------------
; Second way:
; Write:
lmsw reg
;
smsw reg
</syntaxhighlight>
====CR1====
Reserved, the
====CR2====
Line 259 ⟶ 271:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0-31 (63)
|
| Page Fault Linear Address
|-
|}
Line 273 ⟶ 285:
{| {{wikitable}}
|-
!
! Label
! Description
! [[
! [[Long Mode]]
|-
| 3
| PWT
| Page-level Write-Through
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 4
| PCD
| Page-level Cache Disable
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
|
| PDBR
| Page Directory Base Register
|
| Base of PML4T/PML5T
|-
|}
Bits 0-11 of the physical base address are assumed to be 0. Bits 3 and 4 of CR3 are only used when accessing a PDE in 32-bit paging without PAE.
====CR4====
Line 290 ⟶ 316:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
|
|
|-
| 1
|
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|-
| 2
|
| Time Stamp Disable
|-
| 3
|
| Debugging Extensions
|-
| 4
|
| Page Size Extension
|-
| 5
|
| Physical Address Extension
|-
| 6
|
| Machine Check Exception
|-
| 7
|
| Page Global Enabled
|-
| 8
|
| Performance-Monitoring Counter enable
|-
| 9
|
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|-
| 10
| OSXMMEXCPT
| Operating System Support for Unmasked SIMD Floating-Point Exceptions
|-
| 11
|
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|-
| 13
|
| Virtual Machine Extensions Enable
|-
| 14
|
| Safer Mode Extensions Enable
|-
| 16
| FSGSBASE
| Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
|-
| 17
|
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|-
| 18
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|-
| 20
|
| [[Supervisor Memory Protection|Supervisor Mode Execution Protection]] Enable
|-
| 21
|
| [[Supervisor Memory Protection|Supervisor Mode Access Prevention]] Enable
|-
| 22
| PKE
| Protection Key Enable
|-
| 23
| CET
| Control-flow Enforcement Technology
|-
| 24
| PKS
| Enable Protection Keys for Supervisor-Mode Pages
|-
|}
====CR5 - CR7====
Reserved, same case as CR1.
====CR8====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0-3
| TPL
| Task Priority Level
|-
|}
==Extended Control Registers==
====XCR0====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0
| X87
| x87 FPU/MMX support (must be 1)
|-
| 1
| SSE
| XSAVE support for MXCSR and XMM registers
|-
| 2
| AVX
| AVX enabled and XSAVE support for upper halves of YMM registers
|-
| 3
| BNDREG
| MPX enabled and XSAVE support for BND0-BND3 registers
|-
| 4
| BNDCSR
| MPX enabled and XSAVE support for BNDCFGU and BNDSTATUS registers
|-
| 5
| opmask
| AVX-512 enabled and XSAVE support for opmask registers k0-k7
|-
| 6
| ZMM_Hi256
| AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers
|-
| 7
| Hi16_ZMM
| AVX-512 enabled and XSAVE support for upper ZMM registers
|-
| 9
| PKRU
| XSAVE support for PKRU register
|-
|}
XCR0 can only be accessed if bit 18 of CR4 is set to 1. XGETBV and XSETBV instructions are used to access XCR0.
==Debug Registers==
Line 390 ⟶ 495:
{| {{wikitable}}
|-
!
! Description
|-
| 0
|
|-
| 1
|
|-
| 2
|
|-
| 3
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|-
| 4
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|-
| 5
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|-
| 6
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|-
| 7
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|-
| 16-17
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|-
| 18-19
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|-
| 20-21
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|-
| 22-23
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|-
| 24-25
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|-
| 26-27
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|-
| 28-29
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|-
| 30-31
|
|-
|}
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
==Test Registers==
Line 449 ⟶ 554:
{| {{wikitable}}
|-
!
! Description
|-
| TR3 - TR5
| Undocumented
|-
| TR6
|
|-
| TR7
|
|-
|}
Line 469 ⟶ 574:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0-15
|
| (
|-
| 16-47
|
|
|-
|}
Line 488 ⟶ 593:
{| {{wikitable}}
!
!
! Description
|-
| 0-15
|
| (
|-
| 16-47
|
|
|-
|}
Line 507 ⟶ 612:
{| {{wikitable}}
!
!
! Description
|-
| 0-15
|
| (
|-
| 16-47
|
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|-
|}
Stores the segment selector of the [[IDT]].
[[Category:X86 CPU]]
[[Category:CPU_Registers]]
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