CPU Registers x86: Difference between revisions
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Registers described in main "CPU Register" page. |
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== General
{| {{wikitable}}
|-
!
!
!
! 8
! 8 low bits
! Description
|-
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| AL
| Accumulator
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| Base
|-
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| Counter
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| Data
|-
| RSI
| ESI
| SI
| N/A
| SIL
| Source
|-
| RDI
| EDI
| DI
| N/A
| DIL
| Destination
|-
|
| ESP
| SP
| N/A
| SPL
| Stack Pointer
|-
|
| EBP
|
| N/A
| BPL
| Stack Base Pointer
|-
|}
== Pointer Registers ==
{| {{wikitable}}
|-
!
!
! 16-bit
! Description
|-
|
|
| IP
| Instruction Pointer
|-
|}
== Segment Registers ==
{| {{wikitable}}
|-
!
! Description
|-
| CS
| Code Segment
|-
| DS
| Data Segment
|-
| ES
| Extra Segment
|-
|
| Stack Segment
|-
|
| General Purpose F Segment
|-
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| General Purpose G Segment
|-
|}
== EFLAGS
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
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|-
| 2
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|-
| 4
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|-
| 6
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|-
| 7
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| 8
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| 9
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| 10
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| 11
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|-
| 12-13
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|-
| 14
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|-
| 16
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|-
| 17
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|-
| 18
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|-
| 19
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|-
| 20
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|-
| 21
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| Able to use CPUID instruction
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|}
Unlisted bits are reserved.
==Control Registers==
====CR0====
Line 180 ⟶ 197:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
|
| Protected Mode Enable
|-
| 1
|
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|-
| 2
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| x87 FPU Emulation
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| 3
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|-
| 4
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|-
| 5
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|-
| 16
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|-
| 18
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|-
| 29
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|-
| 30
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| 31
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|}
NOTE: This register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction
<syntaxhighlight lang="asm">
; First way:
; Write:
mov cr0, reg
; Read:
mov reg, cr0
; ----------------------
; Second way:
; Write:
lmsw reg
; Read:
smsw reg
</syntaxhighlight>
====CR1====
Reserved, the CPU will throw a #UD exception when trying to access it.
====CR2====
Line 238 ⟶ 271:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0-31 (63)
|
| Page Fault Linear Address
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|}
Line 252 ⟶ 285:
{| {{wikitable}}
|-
!
! Label
! Description
! [[
! [[Long Mode]]
|-
| 3
| PWT
| Page-level Write-Through
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
| 4
| PCD
| Page-level Cache Disable
| (Not used)
| (Not used if bit 17 of CR4 is 1)
|-
|
| PDBR
| Page Directory Base Register
|
| Base of PML4T/PML5T
|-
|}
Bits 0-11 of the physical base address are assumed to be 0. Bits 3 and 4 of CR3 are only used when accessing a PDE in 32-bit paging without PAE.
====CR4====
Line 269 ⟶ 316:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0
|
|
|-
| 1
|
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|-
| 2
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| Time Stamp Disable
|-
| 3
|
| Debugging Extensions
|-
| 4
|
| Page Size Extension
|-
| 5
|
| Physical Address Extension
|-
| 6
|
| Machine Check Exception
|-
| 7
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| Page Global Enabled
|-
| 8
|
| Performance-Monitoring Counter enable
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| 9
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|-
| 10
| OSXMMEXCPT
| Operating System Support for Unmasked SIMD Floating-Point Exceptions
|-
| 11
| UMIP
| User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
|-
| 13
|
| Virtual Machine Extensions Enable
|-
| 14
|
| Safer Mode Extensions Enable
|-
| 16
| FSGSBASE
| Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
|-
| 17
|
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|-
| 18
|
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|-
| 20
|
| [[Supervisor Memory Protection|Supervisor Mode Execution Protection]] Enable
|-
| 21
|
| [[Supervisor Memory Protection|Supervisor Mode Access Prevention]] Enable
|-
| 22
| PKE
| Protection Key Enable
|-
| 23
| CET
| Control-flow Enforcement Technology
|-
| 24
| PKS
| Enable Protection Keys for Supervisor-Mode Pages
|-
|}
==
Reserved, same case as CR1.
====CR8====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0-3
| TPL
| Task Priority Level
|-
|}
==Extended Control Registers==
====XCR0====
{| {{wikitable}}
|-
! Bit
! Label
! Description
|-
| 0
| X87
| x87 FPU/MMX support (must be 1)
|-
| 1
| SSE
| XSAVE support for MXCSR and XMM registers
|-
| 2
| AVX
| AVX enabled and XSAVE support for upper halves of YMM registers
|-
| 3
| BNDREG
| MPX enabled and XSAVE support for BND0-BND3 registers
|-
| 4
| BNDCSR
| MPX enabled and XSAVE support for BNDCFGU and BNDSTATUS registers
|-
| 5
| opmask
| AVX-512 enabled and XSAVE support for opmask registers k0-k7
|-
| 6
| ZMM_Hi256
| AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers
|-
| 7
| Hi16_ZMM
| AVX-512 enabled and XSAVE support for upper ZMM registers
|-
| 9
| PKRU
| XSAVE support for PKRU register
|-
|}
XCR0 can only be accessed if bit 18 of CR4 is set to 1. XGETBV and XSETBV instructions are used to access XCR0.
==Debug Registers==
====DR0 - DR3====
Line 351 ⟶ 484:
====DR6====
It permits the debugger to determine which debug conditions have occurred.
Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.<br>
Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.<br>
Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).<br>
Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.<br>
Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.<br>
====DR7====
Line 357 ⟶ 495:
{| {{wikitable}}
|-
!
! Description
|-
| 0
|
|-
| 1
|
|-
| 2
|
|-
| 3
|
|-
| 4
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|-
| 5
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|-
| 6
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|-
| 7
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|-
| 16-17
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|-
| 18-19
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|-
| 20-21
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|-
| 22-23
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|-
| 24-25
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|-
| 26-27
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|-
| 28-29
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|-
| 30-31
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|-
|}
A local breakpoint bit deactivates on hardware task switches, while a global does not.<br>
==Test
{| {{wikitable}}
|-
!
! Description
|-
| TR3 - TR5
| Undocumented
|-
| TR6
|
|-
| TR7
|
|-
|}
==Protected Mode Registers==
====GDTR====
Line 436 ⟶ 574:
{| {{wikitable}}
|-
!
!
! Description
|-
| 0-15
|
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|-
| 16-47
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|-
|}
Stores the segment selector of the [[GDT]].
====LDTR====
{| {{wikitable}}
! Bits
! Label
! Description
|-
| 0-15
| Limit
| (Size of [[LDT]]) - 1
|-
| 16-47
| Base
| Starting address of [[LDT]]
|-
|}
Stores the segment selector of the [[LDT]].
Line 457 ⟶ 612:
{| {{wikitable}}
!
!
! Description
|-
| 0-15
|
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|-
| 16-47
|
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|-
|}
Stores the segment selector of the [[IDT]].
[[Category:X86 CPU]]
[[Category:CPU_Registers]]
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