ATA PIO Mode: Difference between revisions
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→Control Register bit definitions:: Added reserved bits for completeness. |
→Registers: Added detail to illustrate differences in ports between reads and writes, added table for layout of the Control Register, added description of Error Register and Drive / Head Register |
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===Registers===
An ATA bus typically has 9 I/O ports that control its behavior. For the primary bus, these I/O ports are 0x1F0 through 0x1F7 (the "I/O" ports), and 0x3F6 (
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! Port Offset from
"I/O" base port
! Direction
! Function
! Description
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|-
| 0
| R/W
| Data Register
| Read/Write PIO '''data''' bytes
| 16-bit / 16-bit
|-
| 1
| R
| Error Register
| Used to retrieve any error generated by the last ATA command executed.
| 8-bit / 16-bit
|-
| 1
| W
| Features Register
| Used to control command specific interface features.
| 8-bit / 16-bit
|-
| 2
| R/W
| Sector Count Register
| Number of sectors to read/write (0 is a special value).
| 8-bit / 16-bit
|-
| 3
| R/W
| Sector Number Register (LBAlo)
| This is CHS / LBA28 / LBA48 specific.
| 8-bit / 16-bit
|-
| 4
| R/W
| Cylinder Low Register / (LBAmid)
| Partial Disk Sector address.
| 8-bit / 16-bit
|-
| 5
| R/W
| Cylinder High Register / (LBAhi)
| Partial Disk Sector address.
| 8-bit / 16-bit
|-
| 6
| R/W
| Drive / Head Register
| Used to select a drive and/or head. Supports extra address/flag bits.
| 8-bit / 8-bit
|-
| 7
| R
| Status Register
| Used to read the current status.
| 8-bit / 8-bit
|-
| 7
| W
| Command Register
| Used to send commands.
| 8-bit / 8-bit
|-
|}
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|-
! Port Offset from
"Control" port
! Direction
! Function
! Description
! Param. size LBA28/LBA48
|-
| 0
| R
| Alternate Status Register
| A duplicate of the Status Register which does not affect interrupts.
| 8-bit / 8-bit
|-
| 0
| W
| Command Register
| Used to send ATA commands to the device.
| 8-bit / 8-bit
|-
|}
====Error Register====
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|-
! Bit
! Abbreviation
! Function
|-
| 0
| AMNF
| Address mark not found.
|-
| 1
| TKZNF
| Track zero not found.
|-
| 2
| ABRT
| Aborted command.
|-
| 3
| MCR
| Media change request.
|-
| 4
| IDNF
| ID not found.
|-
| 5
| MC
| Media changed.
|-
| 6
| UNC
| Uncorrectable data error.
|-
| 7
| BBK
| Bad Block detected.
|}
====Drive / Head Register====
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|-
! Bit
! Abbreviation
! Function
|-
| 0 - 3
|
| In CHS addressing, bits 0 to 3 of the head. In LBA addressing, bits 24 to 27 of the block number.
|-
| 4
| DRV
| Selects the drive number.
|-
| 5
| 1
| Always set.
|-
| 6
| LBA
| Uses CHS addressing if clear or LBA addressing if set.
|-
| 7
| 1
| Always set.
|}
====Status Register====
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Technically, when BSY is set, the other bits in the Status byte are meaningless. It is also generally a Bad Idea to test the "Seek Complete" (DSC) bit, because it has been deprecated and replaced by the newer SRV bit.
Reading the Device Control Register port gets you the value of the Alternate Status Register, instead.
The value of Alternate Status is always the same as the Regular Status port (0x1F7 on the Primary bus), but reading the Alternate Status port does not affect interrupts. (See Preempting IRQs, below).
====Device Control Register====
There is an additional IO port that changes the behavior of each ATA bus, called the Device Control Register (on the Primary bus, port 0x3F6). Each ATA bus has its own Control Register.
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