ATA PIO Mode: Difference between revisions

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According to the ATA specs, PIO mode must always be supported by all ATA-compliant drives as the default data transfer mechanism.
 
PIO mode uses a tremendous amount of CPU resources, because every byte of data transferred between the disk and the CPU must be sent through the CPU's [[Inline Assembly/Examples#I\O access|IO port bus]] (not the memory). On some CPUs, PIO mode can still achieve actual transfer speeds of 16MB per sec, but no other processes on the machine will get any CPU time.
 
However, when a computer is just beginning to boot, there are no other processes. So PIO mode is an excellent and simple interface to utilize during bootup, until the system goes into multitasking mode.
 
Please note that this article deals with what are now styled PATA hard disks, as opposed to SATA hard disks.
 
 
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==Master/Slave Drives==
 
There is only one wire dedicated to selecting which drive on each bus is active. It is either electrically "high" or "low", which means that there can never be more than two devices operational on any ATA bus. They are called the master and the slave devices, for no particular reason. TheirThe terms 'master' and 'slave' have largely been abandoned as they inaccurately portray the master drive as having some kind of superiority over the slave drive, or that the latter is dependent on the master. However, these terms will be used in this document. The functionality of the master and slave drives is almost completely identical. There is a special IO port bit that allows a driver to select either drive as the target drive for each command byte.
 
 
 
==Primary/Secondary Bus==
 
Current disk controller chips almost always support two ATA buses per chip. There is a standardized set of IO ports to control the disks on the buses. The first two buses are called the Primary and Secondary ATA bus, and are almost always controlled by IO ports 0x1F0 through 0x1F7, and 0x170 through 0x177, respectively (unless you change it). The associated Device Control Registers/Alternate Status ports are IO ports 0x3F6, and 0x376, respectively. The standard IRQ for the Primary bus is IRQ14, and IRQ15 for the Secondary bus.
 
If the next two buses exist, they are normally controlled by IO ports 0x1E8 through 0x1EF, and 0x168 through 0x16F, respectively. The associated Device Control Registers/Alternate Status ports are IO ports 0x3E6, and 0x366.
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* uint16_t 83: Bit 10 is set if the drive supports LBA48 mode.
 
* uint16_t 88: The bits in the low byte tell you the supported UDMA modes, the upper byte tells you which UDMA mode is active. If the active mode is not the highest supported mode, you may want to figure out why. ''Notes: The returned uint16_t should look like this in binary: 0000001 00000001. Each bit corresponds to a single mode. E.g. if the decimal number is 257, that means that only UDMA mode 1 is supported and running (the binary number above) if the binary number is 515, the binary looks like this, 00000010 00000011, that means that UDMA modes 1 and 2 are supported, and 2 is running. This is true for every mode. If it does not look like that, e.g 00000001 00000011, as stated above, you may want to find out why. The formula for finding out the decimal number is 257 * 2 ^ position + 2 ^position - 1.''
 
* uint16_t 93 from a master drive on the bus: Bit 11 is supposed to be set if the drive detects an 80 conductor cable. ''Notes: if the bit is set then 80 conductor cable is present and UDMA modes > 2 can be used; if bit is clear then there may or may not be an 80 conductor cable and UDMA modes > 2 shouldn't be used but might work fine. Because this bit is "master device only", if there is a slave device and no master there is no way information about cable type (and would have to assume UDMA modes > 2 can't be used).''
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* uint16_t 100 through 103 taken as a uint64_t contain the total number of 48 bit addressable sectors on the drive. (Probably also proof that LBA48 is supported.)
 
 
 
==Addressing Modes==
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(Using a Software Reset -- adapted from PypeClicker)
 
<sourcesyntaxhighlight lang="c">
/* on Primary bus: ctrl->base =0x1F0, ctrl->dev_ctl =0x3F6. REG_CYL_LO=4, REG_CYL_HI=5, REG_DEVSEL=6 */
int detect_devtype (int slavebit, struct DEVICE *ctrl)
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return ATADEV_UNKNOWN;
}
</syntaxhighlight>
</source>
 
 
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(Note: the following routines should all include some form of OS-specific timeout.)
 
<sourcesyntaxhighlight lang="asm">
; do a singletasking PIO ATA read
; inputs: ebx = # of sectors to read, edi -> dest buffer, esi -> driverdata struct, ebp = 4b LBA
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pop eax
ret
</syntaxhighlight>
</source>
 
 
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* [[MBR_(x86)|Master Boot Record (x86)]]
* [[Partition_Table|Partition Table (x86)]]
* [[PCI IDE Controller|IDE Controller]]
 
===Threads===
*[http://www.osdev.org/phpBB2/viewtopic.php?t=12268 How to w/r harddisk in pmode? (ASM Code from Dex)]
*[http://www.osdev.org/phpBB2/viewtopic.php?t=15314 ATA PIO code library (ASM code from XCHG)]
*[http://forum.osdev.org/viewtopic.php?f=1&p=167798#p167798 IDE Tutorial (C code from ''mostafazizo'')]
*[https://forum.osdev.org/viewtopic.php?f=1&t=33152&p=285620#p285620 problem with reading and writing to hard disc (C code for reading/writing with PIO28)]
 
 
===External Links===
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* http://www.ata-atapi.com -- Public Domain C driver sourcecode, including SATA, Busmatering DMA, ATAPI -- not perfect, but good.
* [http://hddguru.com/content/en/documentation/ HDD Guru] -- The actual ATA specs from the first one that was released in 1994 to the 8th one in 2006.
* An exmapleexample of [http://msdn.microsoft.com/en-us/library/windows/hardware/ff559006(v=vs.85).aspx the structure of the data returned by the IDENTIFY Command] (in case you wanted to know what most of the fields were for).
* [http://www.fysnet.net/media_storage_devices.htm A book] written by somebody on the forum about ATA and SATA.
* [https://github.com/omarrx024/xos/blob/master/kernel/blkdev/ata.asm ATA PIO driver in assembly.]