ATA PIO Mode: Difference between revisions

PIO mode uses a tremendous amount of CPU resources, because every byte of data transferred between the disk and the CPU must be sent through the CPU's [[Inline Assembly/Examples#I\O access|IO port bus]] (not the memory). On some CPUs, PIO mode can still achieve actual transfer speeds of 16MB per sec, but no other processes on the machine will get any CPU time.

However, when a computer is just beginning to boot, there are no other processes. So PIO mode is an excellent and simple interface to utilize during bootup, until the system goes into multitasking mode.

There is only one wire dedicated to selecting which drive on each bus is active. It is either electrically "high" or "low", which means that there can never be more than two devices operational on any ATA bus. They are called the master and the slave devices, for no particular reason. TheirThe terms 'master' and 'slave' have largely been abandoned as they inaccurately portray the master drive as having some kind of superiority over the slave drive, or that the latter is dependent on the master. However, these terms will be used in this document. The functionality of the master and slave drives is almost completely identical. There is a special IO port bit that allows a driver to select either drive as the target drive for each command byte.

Current disk controller chips almost always support two ATA buses per chip. There is a standardized set of IO ports to control the disks on the buses. The first two buses are called the Primary and Secondary ATA bus, and are almost always controlled by IO ports 0x1F0 through 0x1F7, and 0x170 through 0x177, respectively (unless you change it). The associated Device Control Registers/Alternate Status ports are IO ports 0x3F6, and 0x376, respectively. The standard IRQ for the Primary bus is IRQ14, and IRQ15 for the Secondary bus.

Which means that a drive select may always happen <i>just before</i> a status read. This is bad. Many drives require a little time to respond to a "select", and push their status onto the bus. The suggestion is to read the Status register <b>FIVEFIFTEEN TIMES</b>, and only pay attention to the value returned by the last one -- after selecting a new master or slave device. The point being that you can assume an IO port read takes approximatelyat 100nsleast 30ns, so doing the first fourfourteen creates a 400ns420ns delay -- which allows the drive time to push the correct voltages onto the bus.

* uint16_t 88: The bits in the low byte tell you the supported UDMA modes, the upper byte tells you which UDMA mode is active. If the active mode is not the highest supported mode, you may want to figure out why. ''Notes: The returned uint16_t should look like this in binary: 0000001 00000001. Each bit corresponds to a single mode. E.g. if the decimal number is 257, that means that only UDMA mode 1 is supported and running (the binary number above) if the binary number is 515, the binary looks like this, 00000010 00000011, that means that UDMA modes 1 and 2 are supported, and 2 is running. This is true for every mode. If it does not look like that, e.g 00000001 00000011, as stated above, you may want to find out why. The formula for finding out the decimal number is 257 * 2 ^ position + 2 ^position - 1.''

An ATA bus typically has 9ten I/O ports thatwhich control its behavior. For the primary bus, these I/O ports are usually 0x1F0 through 0x1F7 (the "I/O" portsport base), through 0x1F7 and 0x3F6 (the "Control" port base). Thethrough values0x3F7. in this table are relative toFor the so-calledsecondary I/Obus, portthey baseare address.usually So0x170 athrough port0x177 offsetand of0x376 1through actually means 0x1F0 + 1 = 0x1F10x377. ThisSome issystems donemay becausehave thenon-standard baseport addresslocations may vary depending onfor the hardware.ATA Alsobusses, somein ofwhich thesecase I/Oit portsmay mapbe helpful to differentconsult registersthe basedsection on whetherPCI theyto aredetermine beinghow readto fromretrieve orport writtenaddresses to.for Seevarious thedevices tablein below for usagethe detailssystem.

! Port Offset from

"I/O" base port

| Used to send ATA commands to the device.

! Port Offset from

"Control" portbase

| CommandDevice Control Register

| Used to sendreset ATAthe commandsbus toor theenable/disable deviceinterrupts.

====Drive / Head Register (I/O base + 6)====

====Status Register (I/O base + 7)====

====Alternate Status Register (Control base + 0)====

====Device Control Register (Control base + 0)====

| Set, then clear (after 5us), this to do a "Software Reset" on all ATA drives on a bus, if one is misbehaving.

<sourcesyntaxhighlight lang="c">

<sourcesyntaxhighlight lang="asm">

*[httphttps://forum.osdev.org/viewtopic.php?f=1&t=33152&p=167798285620#p167798p285620 IDEproblem Tutorialwith reading and writing to hard disc (C code fromfor reading/writing with ''mostafazizo''PIO28)]